 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| mf1213-02 s1d13705f00a technical manual technical manual s1d13705f00a technical manual embedded memory lcd controller s1d13705f00a epson electronic devices website electronic devices marketing division http://www.epson.co.jp/device/ first issue august, 1999 d printed july, 2001 in japan c b this manual was made with recycle papaer, and printed using soy-based inks.
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ms-dos and windows are registered trademarks of microsoft corporation, u.s.a. pc-dos, pc/at, vga, ega and ibm are registered trademarks of international business machines corporation, u.s.a. all other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. seiko epson corporation 2001, all rights reserved. comparison table between new and previous number of evaluation boards s5u 13705 p00c specification corresponding model number (13705: for s1d13705) product classification (s5u: development tool for semiconductor) s1 d 13706 f 00a0 00 the information of the product number change starting april 1, 2001, the product number will be changed as listed below. to order from april 1, 2001 please use the new product number. for further information, please contact epson sales representative. devices configuration of product number comparison table between new and previous number packing specification specification package (b: csp, f: qfp) corresponding model number model name (d: driver, digital products) product classification (s1: semiconductor) evaluation board previous no. sed1335 series sed1335d0a sed1335f0a sed1335f0b s1d13305 series s1d13305d00a s1d13305f00a s1d13305f00b new no. previous no. sed135x series sed1353d0a sed1353f0a sed1353f1a sed1354f0a sed1354f1a sed1354f2a sed1355f0a sed1356f0a s1d1350x series s1d13503d00a s1d13503f00a s1d13503f01a s1d13504f00a s1d13504f01a s1d13504f02a s1d13505f00a s1d13506f00a new no. previous no. sed137x series sed1374f0a sed1375f0a sed1376b0a sed1376f0a sed1378 series s1d1370x series s1d13704f00a s1d13705f00a s1d13706b00a s1d13706f00a s1d13708 series new no. previous no. sed13ax series sed13a3f0a sed13a3b0b sed13a4b0b s1d13a0x series s1d13a03f00a s1d13a03b00b s1d13a04b00b new no. previous no. sed138x series sed1386f0a s1d1380x series s1d13806f00a new no. ?s1d1350x series ?s1d13305 series ?s1d1370x series ?s1d13a0x series ?s1d1380x series ?s1d1350x series ?s1d1370x series ?s1d1380x series ?s1d13a0x series previous no. sdu1353#0c sdu1354#0c sdu1355#0c sdu1356#0c s5u13503p00c s5u13504p00c s5u13505p00c s5u13506p00c new no. previous no. sdu1374#0c sdu1375#0c sdu1376#0c sdu1376bvr sdu1378#0c s5u13704p00c s5u13705p00c s5u13706p00c s5u1370632r s5u13708p00c new no. previous no. sdu1386#0c s5u13806p00c new no. previous no. sdu13a3#0c sdu13a4#0c s5u13a03p00c s5u13a04p00c new no. s1d13705f00a technical manual hardware functional specification programming notes and examples utilities s5u13705b00c isa bus evaluation board user?s manual application notes windows ce display drivers tobira.fm page 1 tuesday, july 24, 2001 10:52 pm s1d13705f00a embedded memory lcd controller hardware functional specification contents s1d13705f00a hardware functional epson 1-i specification contents 1i ntroduction .........................................................................................................................1-1 1.1 scope ....................................................................................................................... .....................1-1 1.2 overview description ........................................................................................................ ............1-1 2f eatures ............................................................................................................................... 1-2 2.1 integrated frame buffer ..................................................................................................... ...........1-2 2.2 cpu interface ............................................................................................................... .................1-2 2.3 display support ............................................................................................................. ................1-2 2.4 display modes ............................................................................................................... ................1-2 2.5 clock source ................................................................................................................ .................1-3 2.6 miscellaneous............................................................................................................... .................1-3 2.7 package ..................................................................................................................... ...................1-3 3t ypical s ystem i mplementation d iagrams ...........................................................................1-4 4f unctional b lock d iagram ..................................................................................................1-7 4.1 functional block descriptions ............................................................................................... ........1-7 4.1.1 host interface............................................................................................................ ....1-7 4.1.2 memory controller ........................................................................................................1 -7 4.1.3 sequence controller .....................................................................................................1- 7 4.1.4 look-up table ............................................................................................................. .1-7 4.1.5 lcd interface ............................................................................................................. ...1-8 4.1.6 power save................................................................................................................ ...1-8 5p ins ............................................................................................................................... ........1-9 5.1 pinout diagram.............................................................................................................. ................1-9 5.2 pin description ............................................................................................................. ...............1-10 5.2.1 host interface............................................................................................................ ..1-10 5.2.2 lcd interface ............................................................................................................. .1-12 5.2.3 clock input ............................................................................................................... ...1-12 5.2.4 miscellaneous ............................................................................................................ 1-12 5.2.5 power supply .............................................................................................................. 1-12 5.3 summary of configuration options ............................................................................................ .1-13 5.4 host bus interface pin mapping .............................................................................................. ....1-13 5.5 lcd interface pin mapping ................................................................................................... ......1-14 6 d.c. c haracteristics .........................................................................................................1-15 7 a.c. c haracteristics .........................................................................................................1-17 7.1 bus interface timing ........................................................................................................ ...........1-17 7.1.1 sh-4 interface timing .................................................................................................1-17 7.1.2 sh-3 interface timing .................................................................................................1-19 7.1.3 motorola mc68k #1 interface timing .........................................................................1-20 7.1.4 motorola mc68k #2 interface timing .........................................................................1-21 7.1.5 generic #1 interface timing........................................................................................1-22 7.1.6 generic #2 interface timing........................................................................................1-23 7.2 clock input requirements .................................................................................................... .......1-24 7.3 display interface........................................................................................................... ...............1-25 7.3.1 power on/reset timing ..............................................................................................1-25 7.3.2 power down/up timing ..............................................................................................1-26 7.3.3 4-bit single monochrome panel timing......................................................................1-27 7.3.4 8-bit single monochrome panel timing......................................................................1-29 7.3.5 4-bit single color panel timing ..................................................................................1-31 7.3.6 8-bit single color panel timing (format 1) ................................................................1-33 7.3.7 8-bit single color panel timing (format 2) ................................................................1-35 7.3.8 8-bit dual monochrome panel timing ........................................................................1-37 7.3.9 8-bit dual color panel timing.....................................................................................1-39 7.3.10 12-bit tft/d-tfd panel timing .................................................................................1-41 contents 1-ii epson s1d13705f00a hardware functional specification 8r egisters ............................................................................................................................1-4 4 8.1 register mapping ............................................................................................................ ............ 1-44 8.2 register descriptions ....................................................................................................... ........... 1-44 9f rame r ate c alculation ....................................................................................................1-56 10 d isplay d ata f ormats ........................................................................................................1-57 11 l ook -u p t able a rchitecture .............................................................................................1-58 11.1 monochrome modes ........................................................................................................... ........ 1-58 11.1.1 1 bit-per-pixel monochrome mode.............................................................................. 1-58 11.1.2 2 bit-per-pixel monochrome mode.............................................................................. 1-58 11.1.3 4 bit-per-pixel monochrome mode.............................................................................. 1-59 11.2 color modes................................................................................................................ ................ 1-60 11.2.1 1 bit-per-pixel color mode .......................................................................................... 1-60 11.2.2 2 bit-per-pixel color mode .......................................................................................... 1-61 11.2.3 4 bit-per-pixel color mode .......................................................................................... 1-62 11.2.4 8 bit-per-pixel color mode .......................................................................................... 1-63 12 s wivel v iew m ode ................................................................................................................1-64 12.1 default swivelview mode.................................................................................................... ........ 1-64 12.1.1 how to set up default swivelview mode ................................................................... 1-65 12.2 alternate swivelview mode.................................................................................................. ....... 1-66 12.2.1 how to set up alternate swivelview mode ................................................................ 1-67 12.3 comparison between default and alternate swivelview modes ................................................ 1-68 12.4 swivelview mode limitations................................................................................................ ...... 1-68 13 p ower s ave m odes .............................................................................................................1-69 13.1 software power save mode................................................................................................... ..... 1-69 13.2 hardware power save mode ................................................................................................... ... 1-69 13.3 power save mode function summary........................................................................................ 1-6 9 13.4 panel power up/down sequence............................................................................................... 1-70 13.5 turning off bclk between accesses ........................................................................................ 1- 70 13.6 clock requirements......................................................................................................... ........... 1-71 14 m echanical d ata ................................................................................................................1-72 contents s1d13705f00a hardware functional epson 1-iii specification list of figures figure 3-1 typical system diagram (sh-4 bus).................................................................................... 1-4 figure 3-2 typical system diagram (sh-3 bus).................................................................................... 1-4 figure 3-3 typical system diagram (m68k #1 bus) .............................................................................1-5 figure 3-4 typical system diagram (m68k #2 bus) .............................................................................1-5 figure 3-5 typical system diagram (generic #1 bus) ..........................................................................1-6 figure 3-6 typical system diagram (generic #2 bus - e.g. isa bus) ...................................................1-6 figure 4-1 system block diagram showing data paths .......................................................................1-7 figure 5-1 pinout diagram....................................................................................................... ..............1-9 figure 7-1 sh-4 timing .......................................................................................................... .............1-17 figure 7-2 sh-3 bus timing ...................................................................................................... ..........1-19 figure 7-3 mc68k #1 bus timing (mc68000) ....................................................................................1-20 figure 7-4 mc68k #2 timing (mc68030)............................................................................................ 1-21 figure 7-5 generic #1 timing .................................................................................................... ..........1-22 figure 7-6 generic #2 timing .................................................................................................... ..........1-23 figure 7-7 clock input requirements ............................................................................................. .....1-24 figure 7-8 lcd panel power on/reset timing...................................................................................1-2 5 figure 7-9 power down/up timing................................................................................................. .....1-26 figure 7-10 4-bit single monochrome panel timing .............................................................................1-2 7 figure 7-11 4-bit single monochrome panel a.c. timing .....................................................................1-28 figure 7-12 8-bit single monochrome panel timing .............................................................................1-2 9 figure 7-13 8-bit single monochrome panel a.c. timing .....................................................................1-30 figure 7-14 4-bit single color panel timing ..................................................................................... ....1-31 figure 7-15 4-bit single color panel a.c. timing ................................................................................ .1-32 figure 7-16 8-bit single color panel timing (format 1)........................................................................1- 33 figure 7-17 8-bit single color panel a.c. timing (format 1)................................................................1-34 figure 7-18 8-bit single color panel timing (format 2)........................................................................1- 35 figure 7-19 8-bit single color panel a.c. timing (format 2)................................................................1-36 figure 7-20 8-bit dual monochrome panel timing................................................................................1- 37 figure 7-21 8-bit dual monochrome panel a.c. timing........................................................................1-38 figure 7-22 8-bit dual color panel timing ....................................................................................... .....1-39 figure 7-23 8-bit dual color panel a.c. timing .................................................................................. ..1-40 figure 7-24 12-bit tft/d-tfd panel timing....................................................................................... ..1-41 figure 7-25 tft/d-tfd a.c. timing ............................................................................................... ......1-42 figure 8-1 screen-register relationship......................................................................................... ....1-52 figure 10-1 1/2/4/8 bit-per-pixel display data memory organization...................................................1-57 figure 11-1 1 bit-per-pixel monochrome mode data output path ........................................................1-58 figure 11-2 2 bit-per-pixel monochrome mode data output path ........................................................1-58 figure 11-3 4 bit-per-pixel monochrome mode data output path ........................................................1-59 figure 11-4 1 bit-per-pixel color mode data output path.....................................................................1-60 figure 11-5 2 bit-per-pixel color mode data output path.....................................................................1-61 figure 11-6 4 bit-per-pixel color mode data output path.....................................................................1-62 figure 11-7 8 bit-per-pixel color mode data output path.....................................................................1-63 figure 12-1 relationship between the screen image and the image refreshed by s1d13705 in default mode1-64 figure 12-2 relationship between the screen image and the image refreshed by s1d13705 in alternate mode1-66 figure 13-1 panel on/off sequence ............................................................................................... ......1-70 figure 14-1 mechanical drawing qfp14............................................................................................ ...1-72 contents 1-iv epson s1d13705f00a hardware functional specification list of tables table 5-1 host interface pin descriptions....................................................................................... ... 1-10 table 5-2 lcd interface pin descriptions ........................................................................................ .. 1-12 table 5-3 clock input pin description ........................................................................................... ..... 1-12 table 5-4 miscellaneous pin descriptions ........................................................................................ . 1-12 table 5-5 power supply pin descriptions ......................................................................................... . 1-12 table 5-6 summary of power on/reset options ............................................................................... 1-13 table 5-7 host bus interface pin mapping ........................................................................................ 1-13 table 5-8 lcd interface pin mapping ............................................................................................. ... 1-14 table 6-1 absolute maximum ratings .............................................................................................. . 1-15 table 6-2 recommended operating conditions for core vdd = 3.3v ?10%................................... 1-15 table 6-3 input specifications .................................................................................................. .......... 1-15 table 6-4 output specifications ................................................................................................. ........ 1-16 table 7-1 sh-4 timing ........................................................................................................... ............ 1-18 table 7-2 sh-3 bus timing ....................................................................................................... ......... 1-19 table 7-3 mc68k #1 bus timing (mc68000) .................................................................................... 1-20 table 7-4 mc68k #2 timing (mc68030) ........................................................................................... 1- 21 table 7-5 generic #1 timing..................................................................................................... ......... 1-22 table 7-6 generic #2 timing..................................................................................................... ......... 1-23 table 7-7 clock input requirements.............................................................................................. .... 1-24 table 7-8 lcd panel power on/reset timing .................................................................................. 1-25 table 7-9 power down/up timing .................................................................................................. ... 1-26 table 7-10 4-bit single monochrome panel a.c. timing..................................................................... 1-28 table 7-11 8-bit single monochrome panel a.c. timing..................................................................... 1-30 table 7-12 4-bit single color panel a.c. timing ................................................................................. 1-32 table 7-13 8-bit single color panel a.c. timing (format 1) ............................................................... 1-34 table 7-14 8-bit single color panel a.c. timing (format 2) ............................................................... 1-36 table 7-15 8-bit dual monochrome panel a.c. timing ....................................................................... 1-38 table 7-16 8-bit dual color panel a.c. timing................................................................................... . 1-40 table 7-17 tft/d-tfd a.c. timing ................................................................................................ ..... 1-43 table 8-1 panel data format ..................................................................................................... ........ 1-45 table 8-2 gray scale/color mode selection ...................................................................................... 1 -45 table 8-3 high performance selection ............................................................................................ .. 1-46 table 8-4 inverse video mode select options................................................................................... 1- 46 table 8-5 hardware power save/gpio0 operation .......................................................................... 1-47 table 8-6 software power save mode selection............................................................................... 1-47 table 8-7 selection of portrait mode............................................................................................ ...... 1-54 table 8-8 selection of pclk and mclk in portrait mode ................................................................. 1-54 table 12-1 default and alternate swivelview mode comparison........................................................ 1-68 table 13-1 power save mode selection ............................................................................................ .. 1-69 table 13-2 software power save mode summary .............................................................................. 1-69 table 13-3 hardware power save mode summary............................................................................. 1-69 table 13-4 power save mode function summary .............................................................................. 1-69 table 13-5 s1d13705 internal clock requirements............................................................................ 1-71 1: introduction s1d13705f00a hardware functional epson 1-1 specification (x27a-a-001-06) 1i ntroduction 1.1 scope this is the hardware functional speci?ation for the s1d13705 embedded memory lcd controller chip. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences: video subsystem designers and software developers. 1.2 overview description the s1d13705 is a color / monochrome lcd graphics controller with an embedded 80k byte sram display buffer. the high integration of the s1d13705 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as of?e automation equipment, mobile communications devices, and hand-held pcs where board size and battery life are major concerns. products requiring a ?ortrait?display can take advantage of the hardware portrait mode feature of the s1d13705. virtual and split screen are just some of the display modes supported. the above features, combined with the operating system independence of the s1d13705, make it the ideal solution for a wide variety of applications. 2: features 1-2 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 2f eatures 2.1 integrated frame buffer embedded 80k byte sram display buffer. 2.2 cpu interface direct support of the following interfaces: hitachi sh-3. hitachi sh-4. motorola m68k. mpu bus interface using wait# signal. direct memory mapping of internal registers. single level cpu write buffer. registers are mapped into upper 32 bytes of 128k byte address space. the complete 80k byte display buffer is directly and contiguously available through the 17-bit address bus. 2.3 display support 4/8-bit monochrome lcd interface. 4/8-bit color lcd interface. single-panel, single-drive passive displays. dual-panel, dual-drive passive displays. active matrix tft / d-tfd interface register level support for el panels. example resolutions: 640 480 at a color depth of 2 bpp 640 240 at a color depth of 4 bpp 320 240 at a color depth of 8 bpp 2.4 display modes swivelview : direct 90? hardware rotation of display image for portrait mode display 1/2/4 bit-per-pixel (bpp), 2/4/16-level grayscale display. 1/2/4/8 bit-per-pixel, 2/4/16/256-level color display. up to 16 shades of gray by frm on monochrome passive lcd panels; a 256 4 look-up table is used to map 1/2/4 bpp modes into these shades. 256 simultaneous of 4096 colors on color passive and active matrix lcd panels; three 256 4 look-up tables are used to map 1/2/4/8 bpp modes into these colors. split screen display for all landscape panel modes allows two different images to be simulta- neously displayed. virtual display support (displays images larger than the panel size through the use of panning). 2: features s1d13705f00a hardware functional epson 1-3 specification (x27a-a-001-06) 2.5 clock source maximum operating clock (clk) frequency of 25mhz. operating clock (clk) is derived from clki input. clk = clki or clk = clki/2 pixel clock (pclk) and memory clock (mclk) are derived from clk. 2.6 miscellaneous hardware/software video invert. software power save mode. hardware power save mode. lcd power-down sequencing. 5 general purpose input/output pins are available. gpio0 is available if hardware power save is not required. gpio[4:1] are available if upper lcd data pins (fpdat[11:8]) are not required for tft/d- tfd support or hardware inverse video. core operates from 2.7 volts to 3.6 volts. io operates from the core voltage up to 5.5 volts. 2.7 package 80 pin qfp14 package. 3: typical system implementation diagrams 1-4 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 3t ypical s ystem i mplementation d iagrams . figure 3-1 typical system diagram (sh-4 bus) . figure 3-2 typical system diagram (sh-3 bus) s1d13705 fpframe fpshift fpline drdy fpdat[7:0] clki oscillator fpframe fpshift fpline mod d[7:0] 8-bit lcd display sh-4 bus reset# we0# d[15:0] bs# rd/wr# rd# rdy# a[16:0] ckio we0# rd/wr# ab[16:0] db[15:0] we1# bs# rd# cs# bclk wait# reset# csn# we1# lcdpwr s1d13705 fpframe fpshift fpline drdy fpdat[7:4] clki oscillator fpframe fpshift fpline mod d[3:0] 4-bit lcd display sh-3 bus reset# we0# d[15:0] bs# rd/wr# rd# wait# a[16:0] ckio we0# rd/wr# ab[16:0] db[15:0] we1# bs# rd# cs# bclk wait# reset# csn# we1# lcdpwr 3: typical system implementation diagrams s1d13705f00a hardware functional epson 1-5 specification (x27a-a-001-06) . figure 3-3 typical system diagram (m68k #1 bus) . figure 3-4 typical system diagram (m68k #2 bus) s1d13705 fpframe fpshift fpline drdy fpdat[7:4] clki oscillator fpframe fpshift fpline mod d[3:0] 4-bit lcd display mc68000 bus reset# lds# d[15:0] as# r/w# dtack# a[16:1] clk ab0 rd/wr# ab[16:1] db[15:0] we1# bs# cs# bclk wait# reset# a[23:17] fc0, fc1, fc2 decoder uds# lcdpwr s1d13705 fpframe fpshift fpline drdy fpdat[7:0] clki oscillator fpframe fpshift fpline mod d[7:0] 8-bit lcd display mc68030 bus reset# siz0 d[31:16] as# r/w# siz1 dsack1# a[16:0] clk we0# rd/wr# ab[16:0] db[15:0] we1# bs# rd# cs# bclk wait# reset# a[31:17] fc0, fc1, fc2 decoder ds# lcdpwr 3: typical system implementation diagrams 1-6 epson s1d13705f00a hardware functional specification (x27a-a-001-06) . figure 3-5 typical system diagram (generic #1 bus) . figure 3-6 typical system diagram (generic #2 bus - e.g. isa bus) s1d13705 fpframe fpshift fpline drdy fpdat[11:0] clki oscillator fpframe fpshift fpline drdy d[11:0] 12-bit tft display generic #1 bus reset# d[15:0] rd0# wait# a[16:0] bclk rd/wr# ab[16:0] db[15:0] we1# rd cs# bclk wait# reset# csn# we1# lcdpwr we0# we0# bs# rd1# s1d13705 fpframe fpshift fpline drdy fpdat[8:0] clki oscillator fpframe fpshift fpline drdy d[8:0] 9-bit tft display isa bus reset sd[15:0] smemr# iochrdy sa[16:0] bclk ab[16:0] db[15:0] we1# rd# bclk wait# reset# lcdpwr we0# smemw# bs# decoder cs# sa[19:17] refresh sbhe# 4: functional block diagram s1d13705f00a hardware functional epson 1-7 specification (x27a-a-001-06) 4f unctional b lock d iagram figure 4-1 system block diagram showing data paths 4.1 functional block descriptions 4.1.1 host interface the host interface provides the means for the cpu/mpu to communicate with the display buffer and internal registers. 4.1.2 memory controller the memory controller arbitrates between cpu accesses and display refresh accesses. it also generates the necessary signals to control the sram frame buffer. 4.1.3 sequence controller the sequence controller controls data ?w from the memory controller through the look-up table and to the lcd interface. it also generates memory addresses for display refresh accesses. 4.1.4 look-up table the look-up table contains three 256 4 look-up tables or palettes, one for each primary color. in monochrome mode only the green look-up table is used. lcd memory controller 40k 16-bit sram lcd clocks power save register sequence controller look-up i/f generic mpu mc68k sh-3 host i/f bus clock memory clock pixel clock table sh-4 4: functional block diagram 1-8 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 4.1.5 lcd interface the lcd interface performs frame rate modulation for passive lcd panels. it also generates the correct data format and timing control signals for various lcd and tft/d-tfd panels. 4.1.6 power save power save contains the power save mode circuitry. 5: pins s1d13705f00a hardware functional epson 1-9 specification (x27a-a-001-06) 5p ins 5.1 pinout diagram figure 5-1 pinout diagram note: package type: 80 pin surface mount qfp14 1234567891011121314151617181920 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 34 35 36 37 38 39 27 28 29 30 31 32 33 40 s1d13705 iov dd db6 db5 db4 db3 db2 db0 db1 corev dd db8 drdy fpdat7 corev dd gpio0 ab3 v ss ab4 ab5 ab6 ab11 ab14 fpdat11 fpdat10 fpdat9 v ss fpshift iov dd fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 fpline fpframe v ss cnf2 db12 db9 db10 db11 db13 db14 db15 wait# v ss rd/wr# we1# we0# rd# bs# cs# reset# ab0 ab1 ab2 corev dd corev dd lcdpwr ab9 ab10 v ss ab8 v ss fpdat8 fpdat6 testen cnf3 cnf1 cnf0 clki iov dd ab15 ab12 bclk ab13 v ss ab7 ab16 db7 5: pins 1-10 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 5.2 pin description key: 5.2.1 host interface i = input o = output io = bi-directional (input/output) p = power pin c = cmos level input cs = cmos level schmitt input cox = cmos output driver, x denotes driver type (see i ol /i oh in table 6-4: ?utput speci?ations,?on page 1-16) tsx = tri-state cmos output driver, x denotes driver type (see i ol /i oh in table 6-4: ?utput speci?ations,?on page 1-16) cnx = cmos low-noise output driver, x denotes driver type (see i ol /i oh in table 6-4: ?utput speci?ations,?on page 1-16) test = cmos level test input with pull down resistor table 5-1 host interface pin descriptions pin names type pin # cell reset# state description ab0 i 70 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs system address bit 0 (a0). for mc68k #1, this pin inputs the lower data strobe (lds#). for mc68k #2, this pin inputs system address bit 0 (a0). for generic #1, this pin inputs system address bit 0 (a0). for generic #2, this pin inputs system address bit 0 (a0). see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. ab[16:1] i 45, 53, 54, 55, 56, 57, 58, 59, 62, 63, 64, 65, 66, 67, 68, 69 c input these pins input the system address bits 16 through 1 (a[16:1]). db[15:0] io 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19 c/ts2 hi-z these pins have multiple functions. for sh-3/sh-4 mode, these pins are connected to [d15:0]. for mc68k #1, these pins are connected to d[15:0]. for mc68k #2, these pins are connected to d[31:16] for a 32-bit device (e.g. mc68030) or d[15:0] for a 16-bit device (e.g. mc68340). for generic #1, these pins are connected to d[15:0]. for generic #2, these pins are connected to d[15:0]. see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. we0# i 77 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs the write enable signal for the lower data byte (we0#). for mc68k #1, this pin must be tied to io v dd for mc68k #2, this pin inputs the bus size bit 0 (siz0). for generic #1, this pin inputs the write enable signal for the lower data byte (we0#). for generic #2, this pin inputs the write enable signal (we#) see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. 5: pins s1d13705f00a hardware functional epson 1-11 specification (x27a-a-001-06) we1# i 78 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs the write enable signal for the upper data byte (we1#). for mc68k #1, this pin inputs the upper data strobe (uds#). for mc68k #2, this pin inputs the data strobe (ds#). for generic #1, this pin inputs the write enable signal for the upper data byte (we1#). for generic #2, this pin inputs the byte enable signal for the high data byte (bhe#). see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. cs# i 74 c input this pin inputs the chip select signal. bclk i 71 c input this pin inputs the system bus clock. bs# i 75 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs the bus start signal (bs#). for mc68k #1, this pin inputs the address strobe (as#). for mc68k #2, this pin inputs the address strobe (as#). for generic #1, this pin must be tied to v ss . for generic #2, this pin must be tied to io v dd . see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. rd/wr# i 79 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs the rd/wr# signal. the s1d13705 needs this signal for early decode of the bus cycle. for mc68k #1, this pin inputs the r/w# signal. for mc68k #2, this pin inputs the r/w# signal. for generic #1, this pin inputs the read command for the upper data byte (rd1#). for generic #2, this pin must be tied to io v dd . see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. rd# i 76 cs input this pin has multiple functions. for sh-3/sh-4 mode, this pin inputs the read signal (rd#). for mc68k #1, this pin must be tied to io v dd . for mc68k #2, this pin inputs the bus size bit 1 (siz1). for generic #1, this pin inputs the read command for the lower data byte (rd0#). for generic #2, this pin inputs the read command (rd#). see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. wait# o 2 ts2 hi-z this pin has multiple functions. for sh-3 mode, this pin outputs the wait request signal (wait#). for sh-4 mode, this pin outputs the device ready signal (rdy#). for mc68k #1, this pin outputs the data transfer acknowledge sig- nal (dtack#). for mc68k #2, this pin outputs the data transfer and size acknowl- edge bit 1 (dsack1#). for generic #1, this pin outputs the wait signal (wait#). for generic #2, this pin outputs the wait signal (wait#). see table 5-7, ?ost bus interface pin mapping, on page 1-13 for summary. reset# i 73 cs 0 active low input to set all internal registers to the default state and to force all signals to their inactive states. table 5-1 host interface pin descriptions pin names type pin # cell reset# state description 5: pins 1-12 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 5.2.2 lcd interface 5.2.3 clock input 5.2.4 miscellaneous 5.2.5 power supply table 5-2 lcd interface pin descriptions pin name type pin # cell reset# state description fpdat[7:0] o 30, 31, 32, 33, 34, 35, 36, 37 cn3 0 panel data fpdat[10:8] o, io 24, 25, 26 cn3 input these pins have multiple functions. panel data bits [10:8] for tft/d-tfd panels. general purpose input/output pins gpio[3:1]. these pins should be connected to io v dd when unused. see table 5-8, ?cd interface pin mapping, on page 1-14 for summary. fpdat11 o, io 23 cn3 input this pin has multiple functions. panel data bit 11 for tft/d-tfd panels. general purpose input/output pin gpio4. inverse video select pin. this pin should be connected to io v dd when unused. see table 5-8, ?cd interface pin mapping, on page 1-14 for summary. fpframe o 39 cn3 0 frame pulse fpline o 38 cn3 0 line pulse fpshift o 28 cn3 0 shift clock lcdpwr o 43 co1 0 active high lcd power control drdy o 42 cn3 0 this pin has multiple functions. tft/d-tfd display enable (drdy). lcd backplane bias (mod). second shift clock (fpshift2). see table 5-8, ?cd interface pin mapping, on page 1-14 for summary. table 5-3 clock input pin description pin name type pin # driver description clki i 51 c input clock table 5-4 miscellaneous pin descriptions pin name type pin # cell reset# state description cnf[3:0] i 46, 47, 48, 49 c as set by hardware these inputs are used to con?ure the s1d13705 - see table 5- 6, ?ummary of power on/reset options,? on page 1-13. must be connected directly to io v dd or v ss . gpio0 io, i 22 cs/ ts1 input this pin has multiple functions - see reg[03h] bit 2. general purpose input/output pin. hardware power save. testen i 44 test pulled low test enable input. this input must be connected to v ss . table 5-5 power supply pin descriptions pin name type pin # driver description corev dd p 1, 21, 41, 61 p core v dd iov dd p 10, 29, 52 p io v dd v ss p 20, 27, 40, 50, 60, 72, 80 p common v ss 5: pins s1d13705f00a hardware functional epson 1-13 specification (x27a-a-001-06) 5.3 summary of con?uration options 5.4 host bus interface pin mapping table 5-6 summary of power on/reset options con?uration pin power on/reset state 10 cnf3 big endian little endian cnf[2:0] select host bus interface as follows: cnf2 cnf1 cnf0 bs# host bus 0 0 0 x sh-4 interface 0 0 1 x sh-3 interface 0 1 0 x reserved 0 1 1 x mc68k #1, 16-bit 1 0 0 x reserved 1 0 1 x mc68k #2, 16-bit 1100 reserved 1101 reserved 1110 generic #1, 16-bit 1111 generic #2, 16-bit table 5-7 host bus interface pin mapping s1d13705 pin names sh-3 sh-4 mc68k #1 mc68k #2 generic #1 generic #2 ab[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] ab0 a0 a0 lds# a0 a0 a0 db[15:0] d[15:0] d[15:0] d[15:0] d[31:16] d[15:0] d[15:0] we1# we1# we1# uds# ds# we1# bhe# cs# csn# csn# external decode external decode external decode external decode bclk ckio ckio clk clk bclk bclk bs# bs# bs# as# as# connect to v ss connect to io v dd rd/wr# rd/wr# rd/wr# r/w# r/w# rd1# connect to io v dd rd# rd# rd# connect to io v dd siz1 rd0# rd# we0# we0# we0# connect to io v dd siz0 we0# we# wait# wait# rdy# dtack# dsack1# wait# wait# reset# reset# reset# reset# reset# reset# reset# 5: pins 1-14 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 5.5 lcd interface pin mapping note: 1. unused gpio pins must be connected to io v dd . 2. hardware video invert is enabled on fpdat11 by reg[02h] bit 1. table 5-8 lcd interface pin mapping s1d13705 pin name monochrome passive panel color passive panel color tft/d-tfd 4-bit single 8-bit single 8-bit dual 4-bit single 8-bit single format 1 8-bit single format 2 8-bit dual 9-bit 12-bit fpframe fpframe fpline fpline fpshift fpshift drdy mod mod mod mod fpshift2 mod mod drdy fpdat0 driven 0 d0 ld0 driven 0 d0 d0 ld0 r2 r3 fpdat1 driven 0 d1 ld1 driven 0 d1 d1 ld1 r1 r2 fpdat2 driven 0 d2 ld2 driven 0 d2 d2 ld2 r0 r1 fpdat3 driven 0 d3 ld3 driven 0 d3 d3 ld3 g2 g3 fpdat4 d0 d4 ud0 d0 d4 d4 ud0 g1 g2 fpdat5 d1 d5 ud1 d1 d5 d5 ud1 g0 g1 fpdat6 d2 d6 ud2 d2 d6 d6 ud2 b2 b3 fpdat7 d3 d7 ud3 d3 d7 d7 ud3 b1 b2 fpdat8 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 b0 b1 fpdat9 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 r0 fpdat10 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 g0 fpdat11 gpio4/ hardware video invert gpio4/ hardware video invert gpio4/ hardware video invert gpio4/ hardware video invert gpio4/ hardware video invert gpio4/ hardware video invert gpio4/ hardware video invert gpio4 b0 6: d.c. characteristics s1d13705f00a hardware functional epson 1-15 specification (x27a-a-001-06) 6 d.c. c haracteristics table 6-1 absolute maximum ratings symbol parameter rating units core v dd supply voltage v ss - 0.3 to 4.0 v io v dd supply voltage core v dd to 7.0 v v in input voltage v ss - 0.3 to io v dd + 0.5 v v out output voltage v ss - 0.3 to io v dd + 0.5 v t stg storage temperature -65 to 150 ? t sol solder temperature/time 260 for 10 sec. max. at lead ? table 6-2 recommended operating conditions for core v dd = 3.3v ?10% symbol parameter condition min. typ. max. units core v dd supply voltage v ss = 0 v 2.7 3.0/3.3 3.6 v io v dd supply voltage v ss = 0 v, io v dd core v dd 2.7 3.0/3.3/5.0 5.5 v v in input voltage v ss io v dd v t opr operating temperature -40 25 85 ? table 6-3 input speci?ations symbol parameter condition min. typ. max. units v il low level input voltage cmos inputs io v dd = 3.0 3.3 5.0 0.8 0.8 1.0 v v v ih high level input voltage cmos inputs io v dd = 3.0 3.3 5.0 1.9 2.0 3.5 v v v t+ positive-going threshold cmos schmitt inputs io v dd = 3.0 3.3 5.0 1.0 1.1 2.0 2.3 2.4 4.0 v v v t- negative-going threshold cmos schmitt inputs io v dd = 3.0 3.3 5.0 0.5 0.6 0.8 1.7 1.8 3.1 v v i iz input leakage current v dd = max. v ih = v dd v il = v ss -1 1 a c in input pin capacitance 10 pf 6: d.c. characteristics 1-16 epson s1d13705f00a hardware functional specification (x27a-a-001-06) table 6-4 output speci?ations symbol parameter condition min. typ. max. units i ol (3.0v) low level output current io v dd = 3.0v v o = 0.4v, type = 1 2 3 1.8 5 10 ma i ol (3.3v) low level output current io v dd = 3.3v v o = 0.4v, type = 1 2 3 2 6 12 ma i ol (5.0v) low level output current io v dd = 5.0v v o = 0.4v, type = 1 2 3 3 8 12 ma i oh (3.0v) high level output current io v dd = 3.0v v o = io v dd - 0.4v,type = 1 2 3 -1.8 -5 -10 ma i oh (3.3v) high level output current io v dd = 3.3v v o = io v dd - 0.4v,type = 1 2 3 -2 -6 -12 ma i oh (5.0v) high level output current io v dd = 5.0v v o = io v dd - 0.4v,type = 1 2 3 -3 -8 -12 ma v ol low level output voltage i = i ol 0.4 v v oh high level output voltage i = i oh io v dd - 0.4 v i oz output leakage current v dd = max. v oh = v dd v ol = v ss -1 1 a c out output pin capacitance 10 pf c bid bidirectional pin capaci- tance 10 pf 7: a.c. characteristics s1d13705f00a hardware functional epson 1-17 specification (x27a-a-001-06) 7 a.c. c haracteristics conditions: io v dd = 2.7 v to 5.0 v t a = -40? to 85? t rise and t fall for all inputs must be < 5 nsec (10% ~ 90%) c l = 60pf (bus/mpu interface) c l = 60pf (lcd panel interface) 7.1 bus interface timing 7.1.1 sh-4 interface timing figure 7-1 sh-4 timing note: the sh-4 wait state control register for the area in which the s1d13705 resides must be set to a non-zero value. the sh-4 read-to-write cycle transition must be set to a non-zero value (with reference to busclk). rdy# t ckio t2 t3 t4 t11 t12 t17 t5 t6 t7 t8 t9 t13 t18 t15 t16 ckio a[16:0], m/r# csn# rd/wr# rd# d[15:0] bs# wen# d[15:0] hi-z hi-z hi-z hi-z valid (write) (read) t10 t14 7: a.c. characteristics 1-18 epson s1d13705f00a hardware functional specification (x27a-a-001-06) note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-1 sh-4 timing symbol parameter min. max. units f ckio bus clock frequency 50 mhz t ckio bus clock period 1/f ckio t2 bus clock pulse width low 8 ns t3 bus clock pulse width high 8 ns t4 a[16:0], rd/wr# setup to ckio 0 ns t5 a[16:0], rd/wr# hold from cs# 0 ns t6 bs# setup 5 ns t7 bs# hold 5 ns t8 csn# setup 0 ns t9 falling edge rd# to db[15:0] driven 25 ns t10 ckio to we#, rd# high 1.5 t ckio t11 rising edge csn# to rdy# high impedance t ckio t12 falling edge csn# to rdy# driven 20 ns t13 ckio to rdy# low 20 ns t14 rising edge csn# to rdy# high 16 ns t15 db[15:0] setup to 2 nd ckio after bs# (write cycle) 0ns t16 db[15:0] hold (write cycle) 0 ns t17 db[15:0] valid to rdy# falling edge setup time (read cycle) 0 ns t18 rising edge rd# to db[15:0] high impedance (read cycle) 10 ns 7: a.c. characteristics s1d13705f00a hardware functional epson 1-19 specification (x27a-a-001-06) 7.1.2 sh-3 interface timing figure 7-2 sh-3 bus timing note: the sh-3 wait state control register for the area in which the s1d13705 resides must be set to a non-zero value. note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-2 sh-3 bus timing symbol parameter min. max. units f ckio bus clock frequency 50 mhz t ckio bus clock period 1/f ckio t2 bus clock pulse width low 8 ns t3 bus clock pulse width high 8 ns t4 a[16:0], rd/wr# setup to ckio 0 ns t5 a[16:0], rd/wr# hold from cs# 0 ns t6 bs# setup 5 ns t7 bs# hold 5 ns t8 csn# setup 0 ns t9 falling edge rd# to db[15:0] driven 25 ns t10 ckio to wen#, rd#high 1.5 t ckio t11 rising edge csn# to wait# high impedance 10 ns t12 falling edge csn# to wait# driven 15 ns t13 ckio to wait# delay 20 ns t14 db[15:0] setup to 2 nd ckio after bs# (write cycle) 0ns t15 db[15:0] hold from rising edge of wen# (write cycle) 0 ns t16 db[15:0] valid to wait# rising edge setup time (read cycle) 0 ns t17 rising edge rd# to db[15:0] high impedance (read cycle) 10 ns t ckio t2 t3 t4 t11 t12 t16 t5 t6 t7 t8 t9 t13 t17 t14 t15 ckio a[16:0], m/r# csn# rd/wr# rd# d[15:0] bs# wait# wen# d[15:0] hi-z hi-z hi-z hi-z hi-z hi-z valid (write) (read) t10 7: a.c. characteristics 1-20 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 7.1.3 motorola mc68k #1 interface timing figure 7-3 mc68k #1 bus timing (mc68000) note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-3 mc68k #1 bus timing (mc68000) symbol parameter min. max. units f clk bus clock frequency 33 mhz t clk bus clock period 1/f clk t1 a[16:1], cs# valid before as# falling edge 0 ns t2 a[16:1], cs# hold from as# rising edge 0 ns t3 as# low to dtack# driven high 16 ns t4 clk to dtack# low 15 ns t5 clk to as#, uds#, lds# high 1 t clk t6 as# high to dtack# high 20 ns t7 as# high to dtack# high impedance t clk t8 uds#, lds# falling edge to d[15:0] valid (write cycle) t clk t9 d[15:0] hold from as# rising edge (write cycle) 0 ns t10 uds#, lds# falling edge to d[15:0] driven (read cycle) 15 ns t11 d[15:0] valid to dtack# falling edge (read cycle) 0 ns t12 uds#, lds# rising edge to d[15:0] high impedance 10 ns t3 a[16:1] as# uds#, lds# valid valid t1 t9 t2 t8 r/w# hi-z hi-z invalid t6 t4 dtack# hi-z hi-z clk t7 t clk cs# t10 t11 hi-z valid hi-z d[15:0] d[15:0] t12 (write (read) t5 7: a.c. characteristics s1d13705f00a hardware functional epson 1-21 specification (x27a-a-001-06) 7.1.4 motorola mc68k #2 interface timing figure 7-4 mc68k #2 timing (mc68030) note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-4 mc68k #2 timing (mc68030) symbol parameter min. max. units f clk bus clock frequency 33 mhz t clk bus clock period 1/f clk t1 a[16:0], cs#, siz0, siz1 valid before as# falling edge 0 ns t2 a[16:0], cs#, siz0, siz1 hold from as#, ds# rising edge 0 ns t3 as# low to dsack1# driven high 22 ns t4 clk to dsack1# low 18 ns t5 clk to as#, ds# high 1 t clk ns t6 as# high to dsack1# high 20 ns t7 as# high to dsack1# high impedance t clk t8 ds# falling edge to d[31:16] valid (write cycle) t clk /2 t9 as#, ds# rising edge to d[31:16] invalid (write cycle) 0 ns t10 d[31:16] valid to dsack1# low (read cycle) 0 ns t11 as#, ds# rising edge to d[31:16] high impedance 20 ns a[16:0] as# ds# valid t1 t9 t2 t8 r/w# hi-z cs# siz0, siz1 clk t6 t3 t4 dsack1# hi-z hi-z t7 t clk t10 valid hi-z hi-z d[31:16] d[31:16] valid hi-z t11 (write) (read) t5 7: a.c. characteristics 1-22 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 7.1.5 generic #1 interface timing figure 7-5 generic #1 timing note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-5 generic #1 timing symbol parameter min. max. units f bclk bus clock frequency 50 mhz t bclk bus clock period 1/f bclk mhz t1 a[16:0], cs# valid to we0#, we1# low (write cycle) or rd0#, rd1# low (read cycle) 0ns t2 we0#, we1# high (write cycle) or rd0#, rd1# high (read cycle) to a[16:0], cs# invalid 0ns t3 we0#, we1# low to d[15:0] valid (write cycle) t bclk t4 rd0#, rd1# low to d[15:0] driven (read cycle) 17 ns t5 we0#, we1# high to d[15:0] invalid (write cycle) 0 ns t6 d[15:0] valid to wait# high (read cycle) 0 ns t7 rd0#, rd1# high to d[15:0] high impedance (read cycle) 10 ns t8 we0#, we1# low (write cycle) or rd0#, rd1# low (read cycle) to wait# driven low 16 ns t9 bclk to wait# high 16 ns t10 we0#, we1# high (write cycle) or rd0#, rd1# high (read cycle) to wait# high impedance 16 ns t11 wait# high to we0#, we1#, rd0#, rd1# high 1 t bclk t bclk t8 t5 t9 t3 t1 t10 bclk a[16:0] cs# we0#,we1# wait# valid t2 hi-z hi-z hi-z valid t6 t7 valid hi-z hi-z d[15:0] d[15:0] t4 rd0#, rd1# (write) (read) t11 7: a.c. characteristics s1d13705f00a hardware functional epson 1-23 specification (x27a-a-001-06) 7.1.6 generic #2 interface timing figure 7-6 generic #2 timing note: ckio may be turned off (held low) between accesses - see section 13.5 ?urning off bclk between accesses?on page 1-70. table 7-6 generic #2 timing symbol parameter min. max. units f bclk bus clock frequency 50 mhz t bclk bus clock period 1/f bclk t1 a[16:0], bhe#, cs# valid to we#, rd# low 0 ns t2 we#, rd# high to a[16:0], bhe#, cs# invalid 0ns t3 we# low to d[15:0] valid (write cycle) t bclk t4 we# high to d[15:0] invalid (write cycle) 0 ns t5 rd# low to d[15:0] driven (read cycle) 16 ns t6 d[15:0] valid to wait# high (read cycle) 0 ns t7 rd# high to d[15:0] high impedance (read cycle) 10 ns t8 we#, rd# low to wait# driven low 14 ns t9 bclk to wait# high 10 ns t10 we#, rd# high to wait# high impedance 11 ns t11 wait# high to we#, rd# high 1 t bclk t8 t4 t9 t3 t1 t10 bclk a[16:0] cs# we#,rd# wait# valid t2 hi-z hi-z hi-z valid t bclk t6 t7 valid hi-z hi-z d[15:0] d[15:0] t5 bhe# (write) (read) t11 7: a.c. characteristics 1-24 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 7.2 clock input requirements figure 7-7 clock input requirements note: when clki is > 25mhz it must be divided by 2 (reg[02h] bit 4 = 1). table 7-7 clock input requirements symbol parameter min. max. units f clki input clock frequency (clki) 0 50 mhz t clki input clock period (clki) 1/f clki t pwh input clock pulse width high (clki) 8 ns t pwl input clock pulse width low (clki) 8 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns t pwl t pwh t f clock input waveform t r t clki v ih v il 10% 90% 7: a.c. characteristics s1d13705f00a hardware functional epson 1-25 specification (x27a-a-001-06) 7.3 display interface 7.3.1 power on/reset timing figure 7-8 lcd panel power on/reset timing note: where t fpframe is the period of fpframe and t pclk is the period of the pixel clock. table 7-8 lcd panel power on/reset timing symbol parameter min. typ. max. units t1 reg[03h] to fpline, fpframe, fpshift, fpdat, drdy active t fpframe ns t2 fpline, fpframe, fpshift, fpdat, drdy active to lcdpwr 0 frames reset# reg[03h] bits [1:0] lcdpwr fpline fpshift fpdat drdy t1 t2 00 11 fpframe active 7: a.c. characteristics 1-26 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 7.3.2 power down/up timing figure 7-9 power down/up timing table 7-9 power down/up timing symbol parameter min. typ. max. units t1 hw power save active to fpline, fpframe, fpshift, fpdat, drdy inactive - lcdpwr override = 1 1 frame t2 hw power save inactive to fpline, fpframe, fpshift, fpdat, drdy active - lcdpwr override = 1 1 frame t3 hw power save active to fpline, fpframe, fpshift, fpdat, drdy inactive - lcdpwr override = 0 1 frame t4 lcdpwr low to fpline, fpframe, fpshift, fpdat, drdy inactive - lcdpwr override = 0 127 frame t5 hw power save inactive to fpline, fpframe, fpshift, fpdat, drdy, lcdpwr active - lcdpwr override = 0 0 frame t6 lcdpwr override active (1) to lcdpwr inactive 1 frame t7 lcdpwr override inactive (1) to lcdpwr active 1 frame t4 t3 t1 active inactive active inactive active lcdpwr override (reg[03h] bit 3) hw power save fp signals lcdpwr t2 software power save 11 00 11 00 11 t5 t6 t7 reg[03h] bits [1:0] or 7: a.c. characteristics s1d13705f00a hardware functional epson 1-27 specification (x27a-a-001-06) 7.3.3 4-bit single monochrome panel timing figure 7-10 4-bit single monochrome panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpshift line1 line2 line3 line4 line239 line240 fpframe line1 line2 fpline drdy (mod) 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 1-1 1-5 1-317 drdy (mod) vndp hdp hndp * diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel fpdat[7:4]] fpdat6 fpdat5 fpdat4 fpdat7 for this timing diagram mask fpshift, reg[01h] bit 3, is set to 1 7: a.c. characteristics 1-28 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-11 4-bit single monochrome panel a.c. timing 1.ts = pixel clock period 2.t1 min = t3 min - 9ts 3.t3 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8]ts 4.t6 min = [(reg[08h] bits 4-0) 8 + 2]ts 5.t7 min = [(reg[08h] bits 4-0) 8 + 11]ts table 7-10 4-bit single monochrome panel a.c. timing symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse rising edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 4 t7 shift pulse falling edge to line pulse falling edge note 5 t8 line pulse falling edge to shift pulse falling edge t14 + 2 ts t9 shift pulse period 4 ts t10 shift pulse pulse width low 2 ts t11 shift pulse pulse width high 2 ts t12 fpdat[7:4] setup to shift pulse falling edge 2 ts t13 fpdat[7:4] hold to shift pulse falling edge 2 ts t14 line pulse falling edge to shift pulse rising edge 23 ts frame pulse line pulse drdy (mod) sync timing line pulse shift pulse fpdat[7:4] data timing t12 t13 t14 t10 t11 t5 t1 t2 t3 t4 t8 t9 12 t7 t6 note: for this timing diagram mask fpshift, reg[01h] bit 3, is set to 1 7: a.c. characteristics s1d13705f00a hardware functional epson 1-29 specification (x27a-a-001-06) 7.3.4 8-bit single monochrome panel timing figure 7-12 8-bit single monochrome panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts hndp vdp fpline fpshift line1 line2 line3 line4 line479 line480 fpframe line1 line2 fpline drdy (mod) 1-2 1-10 1-634 1-3 1-11 1-635 1-4 1-12 1-636 1-5 1-13 1-637 1-6 1-14 1-638 1-7 1-15 1-639 1-8 1-16 1-640 1-1 1-9 1-633 drdy (mod) vndp hdp * diagram drawn with 2 fpline vertical blank period example timing for a 640 480 panel fpdat[7:0] fpdat6 fpdat5 fpdat4 fpdat7 fpdat2 fpdat1 fpdat0 fpdat3 for this timing diagram mask fpshift, reg[01h] bit 3, is set to 1 7: a.c. characteristics 1-30 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-13 8-bit single monochrome panel a.c. timing 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8]ts 4. t6 min = [(reg[08h] bits 4-0) 8 + 4]ts 5. t7 min = [(reg[08h] bits 4-0) 8 + 13]ts table 7-11 8-bit single monochrome panel a.c. timing symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse rising edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 4 t7 shift pulse falling edge to line pulse falling edge note 5 t8 line pulse falling edge to shift pulse falling edge t14 + 4 ts t9 shift pulse period 8 ts t10 shift pulse pulse width low 4 ts t11 shift pulse pulse width high 4 ts t12 fpdat[7:0] setup to shift pulse falling edge 4 ts t13 fpdat[7:0] hold to shift pulse falling edge 4 ts t14 line pulse falling edge to shift pulse rising edge 23 ts t12 t13 frame pulse line pulse drdy (mod) sync timing line pulse shift pulse fpdat[7:0] data timing t5 t1 t2 t3 t4 t14 t8 t9 t10 t11 12 t7 t6 note: for this timing diagram mask fpshift, reg[01h] bit 3, is set to 1 7: a.c. characteristics s1d13705f00a hardware functional epson 1-31 specification (x27a-a-001-06) 7.3.5 4-bit single color panel timing figure 7-14 4-bit single color panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpdat[7:4] line1 line2 line3 line4 line239 line240 fpframe line1 line2 fpline drdy (mod) fpdat6 fpdat5 fpdat4 fpdat7 drdy (mod) vndp 1-r1 1-g1 1-b1 1-r2 1-g2 1-b2 1-r3 1-g3 1-b3 1-r4 1-g4 1-b4 1-b319 1-r320 1-g320 1-b320 hdp hndp * diagram drawn with 2 fpline vertical blank period example timing for a 320 240 panel fpshift 7: a.c. characteristics 1-32 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-15 4-bit single color panel a.c. timing 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8]ts 4. t6 min = [(reg[08h] bits 4-0) 8 + 0.5]ts 5. t7 min = [(reg[08h] bits 4-0) 8 + 9.5]ts table 7-12 4-bit single color panel a.c. timing symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse rising edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 4 t7 shift pulse falling edge to line pulse falling edge note 5 t8 line pulse falling edge to shift pulse falling edge t14 + 0.5 ts t9 shift pulse period 1 ts t10 shift pulse pulse width low 0.5 ts t11 shift pulse pulse width high 0.5 ts t12 fpdat[7:4] setup to shift pulse falling edge 0.5 ts t13 fpdat[7:4] hold to shift pulse falling edge 0.5 ts t14 line pulse falling edge to shift pulse rising edge 23 ts frame pulse line pulse drdy (mod) sync timing line pulse shift pulse fpdat[7:4] data timing t5 t14 t1 t2 t3 t4 t8 t9 t10 t11 t12 t13 12 t7 t6 7: a.c. characteristics s1d13705f00a hardware functional epson 1-33 specification (x27a-a-001-06) 7.3.6 8-bit single color panel timing (format 1) figure 7-16 8-bit single color panel timing (format 1) vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpshift 2 line1 line2 line3 line4 line479 line480 fpframe line1 line2 fpline fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 fpdat7 hdp vndp 1-r1 1-b1 1-g2 1-r3 1-b3 1-g4 1-r5 1-b5 1-g1 1-r2 1-b2 1-g3 1-r4 1-b4 1-g5 1-r6 1-g6 1-r7 1-b7 1-g8 1-r9 1-b9 1-g10 1-r11 1-b6 1-g7 1-r8 1-b8 1-g9 1-r10 1-b10 1-g11 1-r636 1-b636 1-g637 1-r638 1-b638 1-g639 1-r640 1-b640 fpshift 1-b11 1-g12 1-r13 1-b13 1-g14 1-r15 1-b15 1-g16 1-r12 1-b12 1-g13 1-r14 1-b14 1-g15 1-r16 1-b16 hndp * diagram drawn with 2 fpline vertical blank period example timing for a 640 480 panel fpdat[7:0] 7: a.c. characteristics 1-34 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-17 8-bit single color panel a.c. timing (format 1) 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8]ts 4. t6a min = [(reg[08h] bits 4-0) 8 + t13 - t10]ts 5. t6b min = [(reg[08h] bits 4-0) 8 + t13]ts 6. t7a min = [(reg[08h] bits 4-0) 8 + 11]ts 7. t7b min = [(reg[08h] bits 4-0) 8 + 11] - t10]ts table 7-13 8-bit single color panel a.c. timing (format 1) symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t6a shift pulse falling edge to line pulse rising edge note 4 t6b shift pulse 2 falling edge to line pulse rising edge note 5 t7a shift pulse 2 falling edge to line pulse falling edge note 6 t7b shift pulse falling edge to line pulse falling edge note 7 t8 line pulse falling edge to shift pulse rising, shift pulse 2 falling edge t14 + 2 ts t9 shift pulse 2, shift pulse period 4 ts t10 shift pulse 2, shift pulse pulse width low 2 ts t11 shift pulse 2, shift pulse pulse width high 2 ts t12 fpdat[7:0] setup to shift pulse 2, shift pulse falling edge 1 ts t13 fpdat[7:0] hold from shift pulse 2, shift pulse falling edge 1 ts t14 line pulse falling edge to shift pulse rising edge 23 ts frame pulse line pulse sync timing line pulse shift pulse 2 fpdat[7:0] data timing t14 t1 t2 t3 t4 t8 t9 t10 t11 t12 t13 12 t7a t6b shift pulse t6a t7b t12 t13 7: a.c. characteristics s1d13705f00a hardware functional epson 1-35 specification (x27a-a-001-06) 7.3.7 8-bit single color panel timing (format 2) figure 7-18 8-bit single color panel timing (format 2) vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpdat[7:0] line1 line2 line3 line4 line479 line480 fpframe line1 line2 fpline drdy (mod) fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 fpdat7 drdy (mod) vndp 1-r1 1-g1 1-b1 1-r2 1-g2 1-b 2 1-r3 1-g3 1-b3 1-r4 1-g4 1-b4 1-r5 1-g5 1-b5 1-r6 1-g6 1-b6 1-r7 1-g7 1-b7 1-r8 1-g8 1-b8 1-g638 1-b638 1-r639 1-g639 1-b639 1-r640 1-g640 1-b640 hdp hndp * diagram drawn with 2 fpline vertical blank period example timing for a 640 480 panel fpshift 7: a.c. characteristics 1-36 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-19 8-bit single color panel a.c. timing (format 2) 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8]ts 4. t6 min = [(reg[08h] bits 4-0) 8 + 1]ts 5. t7 min = [(reg[08h] bits 4-0) 8 + 10]ts table 7-14 8-bit single color panel a.c. timing (format 2) symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse rising edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 4 t7 shift pulse falling edge to line pulse falling edge note 5 t8 line pulse falling edge to shift pulse falling edge t14 + 2 ts t9 shift pulse period 2 ts t10 shift pulse pulse width low 1 ts t11 shift pulse pulse width high 1 ts t12 fpdat[7:0] setup to shift pulse falling edge 1 ts t13 fpdat[7:0] hold to shift pulse falling edge 1 ts t14 line pulse falling edge to shift pulse rising edge 23 ts t14 t10 t11 t12 t13 data timing frame pulse t1 t2 t3 t5 t4 line pulse drdy (mod) sync timing line pulse shift pulse t8 t9 12 t7 t6 fpdat[7:0] 7: a.c. characteristics s1d13705f00a hardware functional epson 1-37 specification (x27a-a-001-06) 7.3.8 8-bit dual monochrome panel timing figure 7-20 8-bit dual monochrome panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpshift fpdat[7:0] fpframe fpline drdy (mod) fpdat6 1-2 1-6 1-638 fpdat5 1-3 1-7 1-639 fpdat4 1-4 1-8 1-640 fpdat3 241-1 241-5 241-637 fpdat2 241-638 fpdat1 241-639 fpdat0 241-640 fpdat7 1-1 1-5 1-637 hdp drdy (mod) 241-2 241-6 241-3 241-7 241-4 241-8 vndp hndp * diagram drawn with 2 fpline vertical blank period example timing for a 640 480 panel line 1/241 line 2/242 line 3/243 line 4/244 line 239/479 line 240/480 line 1/241 line 2/242 7: a.c. characteristics 1-38 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-21 8-bit dual monochrome panel a.c. timing 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [(((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8) 2]ts 5. t6 min = [((reg[08h] bits 4-0) x 2) 8 + 20]ts 6. t7 min = [((reg[08h] bits 4-0) x 2) 8 + 29]ts table 7-15 8-bit dual monochrome panel a.c. timing symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse falling edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 5 t7 shift pulse falling edge to line pulse falling edge note 6 t8 line pulse falling edge to shift pulse falling edge t14 + 4 ts t9 shift pulse period 8 ts t10 shift pulse pulse width low 4 ts t11 shift pulse pulse width high 4 ts t12 fpdat[7:0] setup to shift pulse falling edge 4 ts t13 fpdat[7:0] hold to shift pulse falling edge 4 ts t14 line pulse falling edge to shift pulse rising edge 39 ts t14 t10 t11 t12 t13 data timing frame pulse t1 t2 t3 t5 t4 line pulse drdy (mod) sync timing line pulse shift pulse t8 t9 12 t7 t6 fpdat[7:0] note: for this timing diagram mask fpshift, reg[01h] bit 3, is set to 1 7: a.c. characteristics s1d13705f00a hardware functional epson 1-39 specification (x27a-a-001-06) 7.3.9 8-bit dual color panel timing figure 7-22 8-bit dual color panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = reg[0ah] bits 5-0 lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = (reg[08h] + 4) 8ts vdp fpline fpdat[7:0] fpframe fpline drdy (mod) drdy (mod) vndp 1-r1 1-g1 1-b1 1-r2 1-g2 1-b2 1-r3 1-g3 1-b3 1-r4 1-g4 1-b4 1-r5 1-g5 1-b5 1-r6 1-g6 1-b6 1-r7 1-g7 1-r8 1-g8 1-b8 1-b639 1-r640 1-g640 1-b640 241- b639 241- r640 241- g640 241- b640 241-r1 241-g1 241-b1 241-r2 241-g2 241-b2 241-r3 241-g3 241-b3 241-r4 241-g4 241-b4 241-r5 241-g5 241-b5 241-r6 241-g6 241-b6 241-r7 241-g7 241-b7 241-r8 241-g8 241-b8 1-b7 fpshift hdp hndp * diagram drawn with 2 fpline vertical blank period example timing for a 640 480 panel line 1/241 line 2/242 line 239/479 line 240/480 line 1/241 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 fpdat7 7: a.c. characteristics 1-40 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-23 8-bit dual color panel a.c. timing 1. ts = pixel clock period 2. t1 min = t3 min - 9ts 3. t3 min = [(((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0) + 4) 8) 2]ts 5. t6 min = [((reg[08h] bits 4-0) 2) 8 + 17]ts 6. t7 min = [((reg[08h] bits 4-0) 2) 8 + 26]ts table 7-16 8-bit dual color panel a.c. timing symbol parameter min. typ. max. units t1 frame pulse setup to line pulse falling edge note 2 (note 1) t2 frame pulse hold from line pulse falling edge 9 ts t3 line pulse period note 3 t4 line pulse pulse width 9 ts t5 mod delay from line pulse falling edge 1 ts t6 shift pulse falling edge to line pulse rising edge note 5 t7 shift pulse falling edge to line pulse falling edge note 6 t8 line pulse falling edge to shift pulse falling edge t14 + 1 ts t9 shift pulse period 2 ts t10 shift pulse pulse width low 1 ts t11 shift pulse pulse width high 1 ts t12 fpdat[7:0] setup to shift pulse falling edge 1 ts t13 fpdat[7:0] hold to shift pulse falling edge 1 ts t14 line pulse falling edge to shift pulse rising edge 39 ts t14 t10 t11 t12 t13 data timing frame pulse t1 t2 t3 t5 t4 line pulse drdy (mod) sync timing line pulse shift pulse t8 t9 12 t7 t6 fpdat[7:0] 7: a.c. characteristics s1d13705f00a hardware functional epson 1-41 specification (x27a-a-001-06) 7.3.10 12-bit tft/d-tfd panel timing figure 7-24 12-bit tft/d-tfd panel timing vdp = vertical display period = (reg[06h] bits 1-0, reg[05h] bits 7-0) + 1 lines vndp = vertical non-display period = vndp1 + vndp2 = (reg[0ah] bits 5-0) lines vndp1 =vertical non-display period 1 = reg[09h] bits 5-0 lines vndp2 =vertical non-display period 2 = (reg[0ah] bits 5-0) - (reg[09ah] bits 5-0) lines hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8ts hndp = horizontal non-display period = hndp1 + hndp2 = (reg[08h] + 4) 8ts hndp1= horizontal non-display period 1= ((reg[07h] bits4-0) 8) +16ts hndp2= horizontal non-display period 2 = (((reg[08h] bits4-0) - (reg[07h] bits 4-0)) 8)+16ts fpframe fpline line1 line480 1-1 1-1 1-1 1-2 1-2 1-2 1-640 1-640 1-640 fpline fpshift drdy fpdat[11:0] fpdat[9] fpdat[10] fpdat[11] vdp drdy note: drdy is used to indicate the first pixel example timing for 12-bit 640 480 panel vndp 2 hdp hndp 2 hndp 1 line480 vndp 1 fpdat[8:6] fpdat[4:3] fpdat[2:0] 7: a.c. characteristics 1-42 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 7-25 tft/d-tfd a.c. timing t12 t7 line pulse t8 t6 frame pulse drdy shift pulse 640 t9 line pulse 2 1 639 t13 t2 t3 t16 t4 t5 t14 t15 t1 t11 t10 fpdat[11:0] note: drdy is used to indicate the first pixel t17 7: a.c. characteristics s1d13705f00a hardware functional epson 1-43 specification (x27a-a-001-06) 1. ts = pixel clock period 2. t6 min = [((reg[04h] bits 6-0)+1) 8 + ((reg[08h] bits 4-0)+4) 8] ts 3. t8 min = [((reg[06h] bits 1-0, reg[05h] bits 7-0)+1) + (reg[0ah] bits 6-0)] lines 4. t10 min = [((reg[04h] bits 6-0)+1) 8] ts 5. t14 min = [((reg[04h] bits 6-0)+1) 8] ts 6. t15 min = [(reg[07h] bits 4-0) 8 + 16] ts 7. t17 min = [(reg[08h] bits 4-0) - (reg[07]) 8 + 16] ts table 7-17 tft/d-tfd a.c. timing symbol parameter min. typ. max. units t1 shift pulse period 1 (note 1) t2 shift pulse pulse width high 0.5 ts t3 shift pulse pulse width low 0.5 ts t4 data setup to shift pulse falling edge 0.5 ts t5 data hold from shift pulse falling edge 0.5 ts t6 line pulse cycle time note 2 t7 line pulse pulse width low 9 ts t8 frame pulse cycle time note 3 t9 frame pulse pulse width low 2t6 t10 horizontal display period note 4 t11 line pulse setup to shift pulse falling edge 0.5 ts t12 frame pulse falling edge to line pulse falling edge phase difference t6 - 18ts t13 drdy to shift pulse falling edge setup time 0.5 ts t14 drdy pulse width note 5 t15 drdy falling edge to line pulse falling edge note 6 t16 drdy hold from shift pulse falling edge 0.5 ts t17 line pulse falling edge to drdy active note 7 250 8: registers 1-44 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 8r egisters 8.1 register mapping the s1d13705 registers are located in the upper 32 bytes of the 128k byte s1d13705 address range. the registers are accessible when cs# = 0 and ab[16:0] are in the range 1ffe0h through 1ffffh. 8.2 register descriptions unless speci?d otherwise, all register bits are reset to 0 during power up. all bits marked n/a should be programmed 0. bits 7-2 product code this is a read-only register that indicates the product code of the chip. the product code is 001001. bits 1-0 revision code this is a read-only register that indicates the revision code of the chip. the revision code is 00. bit 7 tft/stn when this bit = 0, stn (passive) panel mode is selected. when this bit = 1, tft/d-tfd panel mode is selected. if tft/d-tfd panel mode is selected, dual/single (reg[01h] bit 6) and color/mono (reg[01h] bit5) are ignored. see table 8-1 for a comprehensive description of panel selection. bit 6 dual/single when this bit = 0, single lcd panel drive is selected. when this bit = 1, dual lcd panel drive is selected. see table 8-1 for a comprehensive description of panel selection. bit 5 color/mono when this bit = 0, monochrome lcd panel drive is selected. when this bit = 1, color lcd panel drive is selected. see table 8-1 for a comprehensive description of panel selection. bit 4 fpline polarity this bit controls the polarity of fpline in tft/d-tfd mode (no effect in passive panel mode). when this bit = 0, fpline is active low. when this bit = 1, fpline is active high. bit 3 fpframe polarity this bit controls the polarity of fpframe in tft/d-tfd mode (no effect in passive panel mode). when this bit = 0, fpframe is active low. when this bit = 1, fpframe is active high. reg[00h] revision code register address = 1ffe0h read only. product code bit 5 product code bit 4 product code bit 3 product code bit 2 product code bit 1 product code bit 0 revision code bit 1 revision code bit 0 reg[01h] mode register 0 address = 1ffe1h read/write. tft/stn dual/single color/mono fpline polar- ity fpframe polarity mask fpshift data width bit 1 data width bit 0 8: registers s1d13705f00a hardware functional epson 1-45 specification (x27a-a-001-06) bit 2 mask fpshift fpshift is masked during non-display periods if either of the following two criteria is met: 1. color passive panel is selected (reg[01h] bit 5 = 1) 2. this bit (reg[01h] bit 2) = 1 bits 1-0 data width bits [1:0] these bits select the display data format. see table 8-1 below for a comprehensive description of panel selection. bits 7-6 bit-per-pixel bits [1:0] these bits select the color or gray-scale depth (display mode). table 8-1 panel data format tft/stn reg[01h] bit 7 color/mono reg[01h] bit 5 dual/single reg[01h] bit 6 data width bit 1 reg[01h] bit 1 data width bit 0 reg[01h] bit 0 function 0 0 0 0 0 mono single 4-bit passive lcd 1 mono single 8-bit passive lcd 1 0 reserved 1 reserved 1 0 0 reserved 1 mono dual 8-bit passive lcd 1 0 reserved 1 reserved 1 0 0 0 color single 4-bit passive lcd 1 color single 8-bit passive lcd format 1 1 0 reserved 1 color single 8-bit passive lcd format 2 1 0 0 reserved 1 color dual 8-bit passive lcd 1 0 reserved 1 reserved 1 x (don t care) 0 9-bit tft/d-tfd panel 1 12-bit tft/d-tfd panel reg[02h] mode register 1 address = 1ffe2h read/write. bit-per-pixel bit 1 bit-per-pixel bit 0 high perfor- mance input clock divide (clki/2) display blank frame repeat hardware video invert enable software video invert table 8-2 gray scale/color mode selection color/mono reg[01h] bit 6 bit-per-pixel bit 1 reg[02h] bit 7 bit-per-pixel bit 0 reg[02h] bit 6 display mode 0 0 0 2 gray scale 1 bit-per-pixel 1 4 gray scale 2 bit-per-pixel 1 0 16 gray scale 4 bit-per-pixel 1 reserved 1 0 0 2 colors 1 bit-per-pixel 1 4 colors 2 bit-per-pixel 1 0 16 colors 4 bit-per-pixel 1 256 colors 8 bit-per-pixel 8: registers 1-46 epson s1d13705f00a hardware functional specification (x27a-a-001-06) bit 5 high performance (landscape modes only) when this bit = 0, the internal memory clock (mclk) is a divided-down version of the pixel clock (pclk). the denominator is dependent on the bit-per-pixel mode - see the table below. when this bit = 1, mclk is ?ed to the same frequency as pclk for all bit-per-pixel modes. this provides a faster screen update performance in 1/2/4 bit-per-pixel modes, but also increases power consumption. this bit can be set to 1 just before a major screen update, then set back to 0 to save power after the update. this bit has no effect in portrait mode. refer to ?eg[1bh] portrait mode register? on page 1-54 for portrait mode clock selection. bit 4 input clock divide when this bit = 0, the operating clock(clk) is the same as the input clock (clki). when this bit = 1, clk = clki/2. in landscape mode pclk=clk and mclk is selected as per table 8-3 . in portrait mode, mclk and pclk are derived from clk as shown in table 8-8, ?elec- tion of pclk and mclk in portrait mode, on page 1-54. bit 3 display blank this bit blanks the display image. when this bit = 1, the display is blanked (fpdat lines to the panel are driven low). when this bit = 0, the display is enabled. bit 2 frame repeat (el support) this feature is used to improve frame rate modulation of el panels. when this bit = 1, an internal frame counter runs from 0 to 3ffffh. when the frame counter rolls over, the modulated image pattern is repeated (every 1 hour when the frame rate is 72hz). when this bit = 0, the modulated image pattern is never repeated. bit 1 hardware video invert enable in passive panel modes (reg[01h] bit 7 = 0) fpdat11 is available as either gpio4 or hardware video invert. when this bit = 1, hardware video invert is enabled via the fpdat11 pin. when this bit = 0, fpdat11 operates as gpio4. see table 8-4 below. note: video data is inverted after the look-up table. bit 0 software video invert when this bit = 1, inverse video mode is selected. when this bit = 0, standard video mode is selected. see table 8-4 below. note: video data is inverted after the look-up table. table 8-3 high performance selection high performance bpp bit 1 bpp bit 0 display modes 0 0 0 mclk = pclk/8 1 bit-per-pixel 1 mclk = pclk/4 2 bit-per-pixel 1 0 mclk = pclk/2 4 bit-per-pixel 1 mclk = pclk 8 bit-per-pixel 1 x x mclk = pclk table 8-4 inverse video mode select options hardware video invert enable software video invert (passive and active panels) fpdat11 (passive panels only) video data 0 0 x normal 0 1 x inverse 1 x 0 normal 1 x 1 inverse 8: registers s1d13705f00a hardware functional epson 1-47 specification (x27a-a-001-06) bit 3 lcdpwr override when this bit = 1, lcdpwr is forced inactive, by-passing the lcd power sequencing. the 127 frame delay between hardware power save and the lcd panel control signals is reduced to a single line. when this bit = 0, lcdpwr is controlled by the power sequenc- ing logic within the s1d13705. see figure 7-9, ?ower down/up timing, on page 1-26 for further information. bit 2 hardware power save enable when this bit = 1 gpio0 is used as the hardware power save input pin. when this bit = 0, gpio0 operates normally. bits 1-0 software power save bits [1: 0] these bits select the power save mode as shown in the following table. refer to section 13 ?ower save modes?on page 1-69 for a complete description of the power save modes. bits 6-0 horizontal panel size bits [6:0] this register determines the horizontal resolution of the panel. this register must be pro- grammed with a value calculated as follows: note: this register must not be set to a value less than 03h. reg[03h] mode register 2 address = 1ffe3h read/write n/a n/a n/a n/a lcdpwr override hardware power save enable software power save bit 1 software power save bit 0 table 8-5 hardware power save/gpio0 operation reset# state hardware power save enable reg[03h] bit 2 gpio0 con? reg[18h] bit 0 gpio0 status/ control reg[19h] bit 0 gpio0 operation 0xxx 1 0 0 reads pin status gpio0 input (high impedance) 1 0 1 0 gpio0 output = 0 1 0 1 1 gpio0 output = 1 11 x x hardware power save input (active high) table 8-6 software power save mode selection bit 1 bit 0 mode 0 0 software power save 0 1 reserved 1 0 reserved 1 1 normal operation reg[04h] horizontal panel size register address = 1ffe4h read/write n/a horizontal panel size bit 6 horizontal panel size bit 5 horizontal panel size bit 4 horizontal panel size bit 3 horizontal panel size bit 2 horizontal panel size bit 1 horizontal panel size bit 0 horizontal panel size register horizontal panel resolution (pixels) 8 --------------------------------------------------------------------------------------- ?? ?? 1 = 8: registers 1-48 epson s1d13705f00a hardware functional specification (x27a-a-001-06) reg[05h] bits 7-0 vertical panel size bits [9:0] reg[06h] bits 1-0 this 10-bit register determines the vertical resolution of the panel. this regis- ter must be programmed with a value calculated as follows.: 3ffh is the maximum value of this register for a vertical resolution of 1024 lines. bits 4-0 fpline start position these bits are used in tft/d-tfd mode to specify the position of the fpline pulse. these bits specify the delay, in 8-pixel resolution, from the end of a line of display data (fpdat) to the leading edge of fpline. this register is effective in tft/d-tfd mode only (reg[01h] bit 7 = 1). this register is programmed as follows: the following constraint must be satis?d: bits 4-0 horizontal non-display period these bits specify the horizontal non-display period in 8-pixel resolution. reg[05h] vertical panel size register (lsb) address = 1ffe5h read/write vertical panel size bit 7 vertical panel size bit 6 vertical panel size bit 5 vertical panel size bit 4 vertical panel size bit 3 vertical panel size bit 2 vertical panel size bit 1 vertical panel size bit 0 reg[06h] vertical panel size register (msb) address = 1ffe6h read/write n/a n/a n/a n/a n/a n/a vertical panel size bit 9 vertical panel size bit 8 reg[07h] fpline start position address = 1ffe7h read/write n/a n/a n/a fpline start position bit 4 fpline start position bit 3 fpline start position bit 2 fpline start position bit 1 fpline start position bit 0 reg[08h] horizontal non-display period address = 1ffe8h read/write n/a n/a n/a horizontal non-display period bit 4 horizontal non-display period bit 3 horizontal non-display period bit 2 horizontal non-display period bit 1 horizontal non-display period bit 0 vertical panel size register vertical panel resolution (lines) 1 = fplineposition pixels () reg 07h [] 2 + () 8 = reg 07h [] reg 08h [] horizontal non-display period (pixels) reg 08h [] 4 + () 8 = 8: registers s1d13705f00a hardware functional epson 1-49 specification (x27a-a-001-06) bits 5-0 fpframe start position these bits are used in tft/d-tfd mode to specify the position of the fpframe pulse. these bits specify the number of lines between the last line of display data (fpdat) and the leading edge of fpframe. this register is effective in tft/d-tfd mode only (reg[01h] bit 7 = 1). this register is programmed as follows: the contents of this register must be greater than zero and less than or equal to the verti- cal non-display period register, i.e. bit 7 vertical non-display status this bit =1 during the vertical non-display period. bits 5-0 vertical non-display period these bits specify the vertical non-display period. this register is programmed as fol- lows: note: this register should be set only once, on power-up during initialization. bits 5-0 mod rate bits [5:0] when the value of this register is 0, the mod output signal toggles every fpframe. for a non-zero value, the value in this register + 1 speci?s the number of fplines between toggles of the mod output signal. these bits are for passive lcd panels only. reg[09h] fpframe start position address = 1ffe9h read/write n/a n/a fpframe start position bit 5 fpframe start position bit 4 fpframe start position bit 3 fpframe start position bit 2 fpframe start position bit 1 fpframe start position bit 0 reg[0ah] vertical non-display period address = 1ffeah read/write vertical non- display status n/a vertical non- display period bit 5 vertical non- display period bit 4 vertical non- display period bit 3 vertical non- display period bit 2 vertical non- display period bit 1 vertical non- display period bit 0 reg[0bh] mod rate register address = 1ffebh read/write n/a n/a mod rate bit 5 mod rate bit 4 mod rate bit 3 mod rate bit 2 mod rate bit 1 mod rate bit 0 fpframeposition lines () reg 09h [] = 1 reg 09h [] reg 0ah [] ? vertical non-display period (lines) reg[0ah] bits [5:0] = 8: registers 1-50 epson s1d13705f00a hardware functional specification (x27a-a-001-06) reg[0dh] bits 7-0 screen 1 start address bits [15:0] reg[0ch] bits 7-0 these bits determine the word address of the start of screen 1 in landscape modes or the byte address of the start of screen 1 in portrait modes. note: for portrait mode the most significant bit (bit 16) is located in reg[10h]. reg[0fh] bits 7-0 screen 2 start address bits [15:0] reg[0eh] bits 7-0 these bits determine the word address of the start of screen 2 in landscape modes only and has no effect in portrait modes. bit 0 screen 1 start address bit 16 this bit is the most signi?ant bit of screen 1 start address for portrait mode. this bit has no effect in landscape mode. reg[0ch] screen 1 start address register (lsb) address = 1ffech read/write screen 1 start address bit 7 screen 1 start address bit 6 screen 1 start address bit 5 screen 1 start address bit 4 screen 1 start address bit 3 screen 1 start address bit 2 screen 1 start address bit 1 screen 1 start address bit 0 reg[0dh] screen 1 start address register (msb) address = 1ffedh read/write screen 1 start address bit 15 screen 1 start address bit 14 screen 1 start address bit 13 screen 1 start address bit 12 screen 1 start address bit 11 screen 1 start address bit 10 screen 1 start address bit 9 screen 1 start address bit 8 reg[0eh] screen 2 start address register (lsb) address = 1ffeeh read/write screen 2 start address bit 7 screen 2 start address bit 6 screen 2 start address bit 5 screen 2 start address bit 4 screen 2 start address bit 3 screen 2 start address bit 2 screen 2 start address bit 1 screen 2 start address bit 0 reg[0fh] screen 2 start address register (msb) address = 1ffefh read/write screen 2 start address bit 15 screen 2 start address bit 14 screen 2 start address bit 13 screen 2 start address bit 12 screen 2 start address bit 11 screen 2 start address bit 10 screen 2 start address bit 9 screen 2 start address bit 8 reg[10h] screen start address over?w register address = 1fff0h read/write n/a n/a n/a n/a n/a n/a n/a screen 1 start address bit 16 8: registers s1d13705f00a hardware functional epson 1-51 specification (x27a-a-001-06) bits 7-0 memory address offset bits [7:0] (landscape modes only) this register is used to create a virtual image by setting a word offset between the last address of one line and the ?st address of the following line. if this register is not equal to zero, then a virtual image is formed. the displayed image is a window into the larger vir- tual image. see figure 8-1, ?creen-register relationship,? on page 1-52. this register has no effect in portrait modes. see ?reg[1ch] line byte count register for portrait mode? on page 1-55. reg[13h] bits 1-0 screen 1 vertical size bits [9:0] reg[12h] bits 7-0 these bits determine the height (in lines) of screen 1. in landscape modes, if this register is programmed with a value, n, where n is less than the vertical panel size (reg[06h], reg[05h]), then lines 0 to n of the panel contain screen 1 and lines n+1 to reg[06h], reg[05h] of the panel contain screen 2. see figure 8-1, ?creen-register relationship,? on page 1-52. in portrait modes this register must be programmed greater than, or equal to the vertical panel size, reg[06h] and reg[05h]. see ?2 swivelview mode? on page 1-64. reg[11h] memory address offset register address = 1fff1h read/write memory address offset bit 7 memory address off- set bit 6 memory address off- set bit 5 memory address off- set bit 4 memory address off- set bit 3 memory address off- set bit 2 memory address off- set bit 1 memory address off- set bit 0 reg[12h] screen 1 vertical size register (lsb) address = 1fff2h read/write screen 1 verti- cal size bit 7 screen 1 verti- cal size bit 6 screen 1 verti- cal size bit 5 screen 1 verti- cal size bit 4 screen 1 verti- cal size bit 3 screen 1 verti- cal size bit 2 screen 1 verti- cal size bit 1 screen 1 verti- cal size bit 0 reg[13h] screen 1 vertical size register (msb) address = 1fff3h read/write n/a n/a n/a n/a n/a n/a screen 1 verti- cal size bit 9 screen 1 verti- cal size bit 8 8: registers 1-52 epson s1d13705f00a hardware functional specification (x27a-a-001-06) figure 8-1 screen-register relationship consider an example where reg[13h], reg[12] = 0ceh for a 320x240 display system. the upper 207 lines (ceh + 1) of the panel show an image from the screen 1 start word address. the remaining 33 lines show an image from the screen 2 start word address. bits 7-0 lut address bits [7:0] these 8 bits control a pointer into the look-up tables (lut). the s1d13705 has three 256-position, 4-bit wide luts, one for each of red, green, and blue ?refer to section 11 ?ook-up table architecture?on page 1-58 for details. this register selects which lut entry is read/write accessible through the lut data reg- ister (reg[17h]). writing the lut address register automatically sets the pointer to the red lut. accesses to the lut data register automatically increment the pointer. for example, writing a value 03h into the lut address register sets the pointer to r[3]. a subsequent access to the lut data register accesses r[3] and moves the pointer onto g[3]. subsequent accesses to the lut data register move the pointer onto b[3], r[4], g[4], b[4], r[5], etc. note: the rgb data is inserted into the lut after the blue data is written, i.e. all three colors must be written before the lut is updated. reg[15h] look-up table address register address = 1fff5h read/write lut address bit 7 lut address bit 6 lut address bit 5 lut address bit 4 lut address bit 3 lut address bit 2 lut address bit 1 lut address bit 0 line 0 line 1 (reg[0dh], reg[0ch]) words line 0 last pixel address + reg[11h] words line 0 last pixel address=((reg[0dh], reg[0ch]) + (8(reg[04h]+1) bpp/16)) 8(reg[04h]+1) pixels virtual image reg[11h] words line=(reg[13h], reg[12h]) ((reg[06h], reg[05])+1) lines image 1 image 2 (reg[0fh], reg[0eh]) words where: (reg[0dh], reg[0ch]) is the screen 1 start word address bpp is bits-per-pixel as set by reg[02h] bits 7:6 reg[11h] is the address pitch adjustment in words (reg[0fh], reg[0eh]) is the screen 2 start word address (reg[13h], reg[12h]) is the screen 1 vertical size (reg[06h], reg[05h]) is the vertical panel size words 8: registers s1d13705f00a hardware functional epson 1-53 specification (x27a-a-001-06) bits 7-4 lut data bits [3:0] this register is used to read/write the rgb look-up tables. this register accesses the entry at the pointer controlled by the look-up table address register (reg[15h]). accesses to the look-up table data register automatically increment the pointer. note: the rgb data is inserted into the lut after the blue data is written, i.e. all three colors must be written before the lut is updated. bits 4-0 gpio[4:0] pin io con?uration these bits determine the direction of the gpio[4:0] pins. when the gpion pin io con?uration bit = 0, the corresponding gpion pin is con?- ured as an input. the input can be read at the gpion status/control register bit. see ?eg[19h] gpio status/control register? when the gpion pin io con?uration bit = 1, the corresponding gpion pin is con?- ured as an output. the output can be controlled by writing the gpion status/control reg- ister bit. note: these bits have no effect when the gpion pin is configured for a specific function (i.e. as fpdat[11:8] for tft/d-tfd operation). when configured as io, all unused pins must be tied to io v dd . bits 4-0 gpio[4:0] status when the gpion pin is con?ured as an input, the corresponding gpio status bit is used to read the pin input. see reg[18h] above. when the gpion pin is con?ured as an output, the corresponding gpio status bit is used to control the pin output. bits 7-0 scratch pad register this register contains general use read/write bits. these bits have no effect on hardware. reg[17h] look-up table data register address = 1fff7h read/write lut data bit 3 lut data bit 2 lut data bit 1 lut data bit 0 n/a n/a n/a n/a reg[18h] gpio con?uration control register address = 1fff8h read/write n/a n/a n/a gpio4 pin io con?uration gpio3 pin io con?uration gpio2 pin io con?uration gpio1 pin io con?uration gpio0 pin io con?uration reg[19h] gpio status/control register address = 1fff9h read/write n/a n/a n/a gpio4 pin io status gpio3 pin io status gpio2 pin io status gpio1 pin io status gpio0 pin io status reg[1ah] scratch pad register address = 1fffah read/write scratch bit 7 scratch bit 6 scratch bit 5 scratch bit 4 scratch bit 3 scratch bit 2 scratch bit 1 scratch bit 0 8: registers 1-54 epson s1d13705f00a hardware functional specification (x27a-a-001-06) bit 7 portrait mode enable when this bit = 1, portrait mode is enabled. when this bit = 0, landscape mode is enabled. bit 6 portrait mode select when this bit = 0, default portrait mode is selected. when this bit = 1, alternate portrait mode is selected. see section 12 ?wivelview mode?on page 1-64 for further informa- tion on portrait mode. the following table shows the selection of portrait mode. bit 2 reserved reserved bits must be set to 0. bits 1-0 portrait mode pixel clock select bits [1:0] these two bits select the pixel clock (pclk) source in portrait mode - these bits have no effect in landscape mode. the following table shows the selection of pclk and mclk in portrait mode - see section 12 ?wivelview mode?on page 1-64 for details. where clk is clki (reg[02h] bit 4 = 0) or clki/2 (reg[02h] bit 4 = 1) reg[1bh] portrait mode register address = 1fffbh read/write portrait mode enable portrait mode select n/a n/a n/a reserved portrait mode pixel clock select bit 1 portrait mode pixel clock select bit 0 table 8-7 selection of portrait mode portrait mode enable (reg[1bh] bit 7) portrait mode select (reg[1bh] bit 6) mode 0 x landscape 1 0 default portrait 1 1 alternate portrait table 8-8 selection of pclk and mclk in portrait mode portrait mode enable (reg[1bh] bit 7) portrait mode select (reg[1bh] bit 6) pixel clock (pclk) select (reg[1bh] bits [1:0] pclk = mclk = bit 1 bit 0 0 x x x clk see reg[02h] bit 5 1 0 0 0 clk clk 1 0 0 1 clk/2 clk/2 1 0 1 0 clk/4 clk/4 1 0 1 1 clk/8 clk/8 1 1 0 0 clk/2 clk 1 1 0 1 clk/2 clk 1 1 1 0 clk/4 clk/2 1 1 1 1 clk/8 clk/4 8: registers s1d13705f00a hardware functional epson 1-55 specification (x27a-a-001-06) bits 7-0 line byte count bits [7:0] this register is the byte count from the beginning of one line to the beginning of the next consecutive line (commonly called ?tride?by programmers). this register may be used to create a virtual image in portrait mode. when this register = 00 the ?tride?= 256 bytes. this value is used for 240 320 8 bpp default portrait mode when the line byte count register = n, where 1 n ffh, the ?tride?= n bytes. reg[1eh] and reg[1fh] reg[1eh] and reg[1fh] are reserved for factory s1d13705 testing and should not be written. any value written to these registers may result in damage to the s1d13705 and/or any panel connected to the s1d13705. reg[1ch] line byte count register for portrait mode address = 1fffch read/write line byte count bit 7 line byte count bit 6 line byte count bit 5 line byte count bit 4 line byte count bit 3 line byte count bit 2 line byte count bit 1 line byte count bit 0 9: frame rate calculation 1-56 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 9f rame r ate c alculation the following formulae are used to calculate the display frame rate. tft/d-tfd and passive single-panel modes where: f pclk = pclk frequency (hz) hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8 pixels hndp = horizontal non-display period = ((reg[08h] bits 4-0) + 4) 8 pixels vdp = vertical display period = ((reg[06h] bits 1-0, reg[05h] bits 7-0) + 1) lines vndp = vertical non-display period = (reg[0ah] bits 5-0) lines passive dual-panel mode where: f pclk = pclk frequency (hz) hdp = horizontal display period = ((reg[04h] bits 6-0) + 1) 8 pixels hndp = horizontal non-display period = ((reg[08h] bits 4-0) + 4) 8 pixels vdp = vertical display period = ((reg[06h] bits 1-0, reg[05h] bits 7-0) + 1) lines vndp = vertical non-display period = (reg[0ah] bits 5-0) lines framerate f pclk hdp hndp + () vdp vndp + () ---------------------------------------------------------------------------------------- - = framerate f pclk 2 hdp hndp + () vdp 2 ------------ vndp + ?? ?? -------------------------------------------------------------------------------------------------- - = 10: display data formats s1d13705f00a hardware functional epson 1-57 specification (x27a-a-001-06) 10 d isplay d ata f ormats figure 10-1 1/2/4/8 bit-per-pixel display data memory organization 1-bpp: a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 host address display memory panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 2-bpp: a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 host address display memory a 4 b 4 a 5 b 5 a 6 b 6 a 7 b 7 bit 7 bit 0 bit 7 bit 0 4-bpp: a 0 b 0 c 0 d 0 a 1 b 1 c 1 d 1 host address display memory a 2 b 2 c 2 d 2 a 3 b 3 c 3 d 3 bit 7 bit 0 a 4 b 4 c 4 d 4 a 5 b 5 c 5 d 5 host address display memory bit 7 bit 0 8-bpp: a 0 b 0 c 0 d 0 e 0 f 0 g 0 h 0 a 1 b 1 c 1 d 1 e 1 f 1 g 1 h 1 a 2 b 2 c 2 d 2 e 2 f 2 g 2 h 2 byte 0 byte 0 byte 1 byte 0 byte 1 byte 2 byte 0 byte 1 byte 2 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = (a n ) p n = (a n , b n ) p n = (a n , b n , c n , d n ) p n = (a n , b n , c n , d n , e n , f n , g n , h n ) 11: look-up table architecture 1-58 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 11 l ook -u p t able a rchitecture the following ?ures are intended to show the display data output path only. note: when video data invert is enabled the video data is inverted after the look-up table. 11.1 monochrome modes the green look-up table (lut) is used for all monochrome modes. 11.1.1 1 bit-per-pixel monochrome mode figure 11-1 1 bit-per-pixel monochrome mode data output path 11.1.2 2 bit-per-pixel monochrome mode figure 11-2 2 bit-per-pixel monochrome mode data output path green look-up table 256 4 00 01 fc fd fe ff 1 bit-per-pixel data 4-bit gray data from display buffer 0 1 02 = unused look-up table entries green look-up table 256 4 00 01 02 03 fc fd fe ff 00 01 2 bit-per-pixel data 4-bit gray data from display buffer 10 11 = unused look-up table entries 04 11: look-up table architecture s1d13705f00a hardware functional epson 1-59 specification (x27a-a-001-06) 11.1.3 4 bit-per-pixel monochrome mode figure 11-3 4 bit-per-pixel monochrome mode data output path green look-up table 256 4 00 01 02 03 fc fd fe ff 0000 0001 4 bit-per-pixel data 4-bit gray data from display buffer 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0a 0b 0c 0d 0e 0f 1000 1001 1010 1011 1100 1101 1110 1111 = unused look-up table entries 10 11: look-up table architecture 1-60 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 11.2 color modes 11.2.1 1 bit-per-pixel color mode figure 11-4 1 bit-per-pixel color mode data output path red look-up table 256 4 00 01 fc fd fe ff 1 bit-per-pixel data from display buffer green look-up table 256 4 00 01 fc fd fe ff blue look-up table 256 4 00 01 fc fd fe ff 0 1 0 1 0 1 4-bit red data 4-bit green data 4-bit blue data = unused look-up table entries 02 02 02 11: look-up table architecture s1d13705f00a hardware functional epson 1-61 specification (x27a-a-001-06) 11.2.2 2 bit-per-pixel color mode figure 11-5 2 bit-per-pixel color mode data output path red look-up table 256 4 00 01 02 03 fc fd fe ff 00 01 2 bit-per-pixel data 4-bit red data from display buffer 10 11 green look-up table 256 4 00 01 02 03 00 01 4-bit green data 10 11 blue look-up table 256 4 00 01 02 03 00 01 4-bit blue data 10 11 = unused look-up table entries 04 04 fc fd fe ff 04 fc fd fe ff 11: look-up table architecture 1-62 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 11.2.3 4 bit-per-pixel color mode figure 11-6 4 bit-per-pixel color mode data output path red look-up table 256 4 00 01 02 03 0000 0001 4 bit-per-pixel data 4-bit red data from display buffer 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0a 0b 0c 0d 0e 0f 1000 1001 1010 1011 1100 1101 1110 1111 green look-up table 256 4 00 01 02 03 0000 0001 4-bit green data 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0a 0b 0c 0d 0e 0f 1000 1001 1010 1011 1100 1101 1110 1111 blue look-up table 256 4 00 01 02 03 0000 0001 4-bit blue data 0010 0011 04 05 06 07 0100 0101 0110 0111 08 09 0a 0b 0c 0d 0e 0f 1000 1001 1010 1011 1100 1101 1110 1111 = unused look-up table entries 10 fc fd fe ff 10 fc fd fe ff 10 fc fd fe ff 11: look-up table architecture s1d13705f00a hardware functional epson 1-63 specification (x27a-a-001-06) 11.2.4 8 bit-per-pixel color mode figure 11-7 8 bit-per-pixel color mode data output path red look-up table 256 4 00 01 02 03 0000 0000 0000 0001 8 bit-per-pixel data 4-bit red data from display buffer 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 f8 f9 fa fb fc fd fe ff 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 green look-up table 256 4 00 01 02 03 0000 0000 0000 0001 4-bit green data 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 f8 f9 fa fb fc fd fe ff 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 blue look-up table 256 4 00 01 02 03 0000 0000 0000 0001 4-bit blue data 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 f8 f9 fa fb fc fd fe ff 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 12: swivelview mode 1-64 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 12 s wivel v iew m ode many of todays applications use the lcd panel in a portrait orientation. in this case it becomes necessary to ?otate?the displayed image by 90?. this rotation can be done by software at the expense of performance or, it can be done by the s1d13705 hardware with no cpu penalty. there are two swivelview modes: default swivelview mode and alternate swivelview mode. 12.1 default swivelview mode default swivelview mode requires the portrait image width be a power of two, e.g. a 240-line panel requires a minimum virtual image width of 256. this mode should be used whenever the required virtual image can be contained within the integrated display buffer (i.e. virtual image size 80k bytes), as it consumes less power than the alternate swivelview mode. for example, the panel size is 320x240 and the display mode is 8 bit-per-pixel. the virtual image size is 320x256 which can be contained within the 80k byte display buffer. default swivelview mode also requires memory clock (mclk) pixel clock (pclk). the following ?ure shows how the programmer sees a 240x320 image and how the image is displayed. the application image is written to the s1d13705 in the following sense: a???. the display is refreshed by the s1d13705 in the following sense: b-d-a-c. figure 12-1 relationship between the screen image and the image refreshed by s1d13705 in default mode 256 256 image seen by programmer = image in display buffer 320 swivelview window 320 240 ab c d d c b a 240 start address swivelview window display e e image refreshed by s1d13705 start address physical memory 12: swivelview mode s1d13705f00a hardware functional epson 1-65 specification (x27a-a-001-06) 12.1.1 how to set up default swivelview mode the following describes the register settings needed to set up default swivelview mode for a 240 320 8 bpp image: select default swivelview mode: reg[1bh] bit 7 = 1 and bit 6 = 0 the display refresh circuitry starts at pixel ?? therefore the screen 1 start address register must be programmed with the address of pixel ?? i.e. the line byte count register for swivelview mode must be set to the virtual-image width in bytes, i.e. panning is achieved by changing the screen 1 start address register: increment the register by 1 to pan horizontally by one byte, e.g. one pixel in 8 bpp mode increment the register by twice the effective value of the line byte count register to pan vertically by two lines, e.g. add 200h to pan by two lines in the example above. note: vertical panning by a single line is not supported in default swivelview mode. reg[10h], reg[0dh], reg[0ch] addressofpixelb = addressofpixela byteoffset + () = addressofpixela 240pixels 8bpp 8bpb -------------------------------------------- ?? ?? 1 + = addressofpixela efh + = where bpp is bits-per-pixel and bpb is bits-per-byte. reg 1ch [] 256 8bpb () 8bpp () ----------------------------------------- - 256 1 -------- - 256 00h : see reg[1ch] for explanation ==== where bpb is bits-per-byte and bpp is bits-per-pixel. 12: swivelview mode 1-66 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 12.2 alternate swivelview mode alternate swivelview mode may be used when the virtual image size of default swivelview mode cannot be contained in the 80k byte integrated frame buffer. for example, the panel size is 480 320 and the display mode is 4 bit-per-pixel. the minimum virtual image size for default swivelview mode would be 480 512 which requires 122,880 bytes. alternate swivelview mode requires a panel size of only 480 320 which needs only 76,800 bytes. alternate swivelview mode requires the memory clock (mclk) to be at least twice the frequency of the pixel clock (pclk), i.e. mclk 2 x pclk. this makes the power consumption in alternate swivelview mode higher than in default swivelview mode. the following ?ure shows how the programmer sees a 480 320 image and how the image is being displayed. the application image is written to the s1d13705 in the following sense: a???. the display is refreshed by the s1d13705 in the following sense: b-d-a-c. figure 12-2 relationship between the screen image and the image refreshed by s1d13705 in alternate mode image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 start address swivelview window display image refreshed by s1d13705 start address physical memory 12: swivelview mode s1d13705f00a hardware functional epson 1-67 specification (x27a-a-001-06) 12.2.1 how to set up alternate swivelview mode the following describes the register settings needed to set up alternate swivelview mode for a 320 480 4 bpp image. select alternate swivelview mode: reg[1bh] bit 7 = 1 and bit 6 = 1 the display refresh circuitry startsp at pixel ?? therefore the screen 1 start address register must be programmed with the address of pixel ?? or the line byte count register for swivelview mode must be set to the image width in bytes, i.e. panning is achieved by changing the screen 1 start address register: increment the register by 1 to pan horizontally by one byte, e.g. two pixels in 4 bpp mode increment the register by the value in the line byte count register to pan vertically by one line, e.g. add a0h to pan by one line in the example above reg[10h], reg[0dh], reg[0ch] address of pixel b = address of pixel a byte offset + () = address of pixel a 320pixels 4bpp 8bpb -------------------------------------------- ?? ?? 1 + = address of pixel a 9fh + = where bpp is bits-per-pixel and bpb is bits-per-byte. reg 1ch [] 320 8bpb () 4bpp () ----------------------------------------- - 320 2 -------- - 160 a0h ==== where bpb is bits-per-byte and bpp is bits-per-pixel. 12: swivelview mode 1-68 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 12.3 comparison between default and alternate swivelview modes 12.4 swivelview mode limitations the only limitation to using swivelview mode on the s1d13705 is that split screen operation is not supported. table 12-1 default and alternate swivelview mode comparison item default swivelview mode alternate swivelview mode memory requirements the width of the rotated image must be a power of 2. in most cases, a virtual image is required where the right-hand side of the virtual image is unused and memory is wasted. for example, a 320 480 4bpp image would normally require only 76,800 bytes - possible within the 80k byte address space, but the virtual image is 512 480 4bpp which needs 122,880 bytes - not possible. does not require a virtual image. clock requirements clk need only be as fast as the required pclk. mclk, and hence clk, need to be 2x pclk. for example, if the panel requires a 3mhz pclk, then clk must be 6mhz. note that 25mhz is the maxi- mum clk, so pclk cannot be higher than 12.5mhz in this mode. power consumption lowest power consumption. higher than default mode. panning vertical panning in 2 line increments. vertical panning in 1 line increments. performance nominal performance. higher performance than default mode. 13: power save modes s1d13705f00a hardware functional epson 1-69 specification (x27a-a-001-06) 13 p ower s ave m odes two power save modes have been incorporated into the s1d13705 to accommodate the need for power reduction in the hand-held devices market. these modes are enabled as follows: 13.1 software power save mode software power save mode saves power by powering down the panel and stopping display refresh accesses to the display buffer. 13.2 hardware power save mode hardware power save mode saves power by powering down the panel, stopping accesses to the display buffer and registers, and disabling the host bus interface. 13.3 power save mode function summary note: when fpdat[11:8] are designated as gpio these pins are not forced low. unused gpio pins must be tied to io v dd - see table 5-8, ?cd interface pin mapping, on page 1-14. table 13-1 power save mode selection hardware power save software power save bit 1 software power save bit 0 mode not con?ured or 0 0 0 software power save mode not con?ured or 0 0 1 reserved not con?ured or 0 1 0 reserved not con?ured or 0 1 1 normal operation con?ured and 1 x x hardware power save mode table 13-2 software power save mode summary registers read/write accessible memory read/write accessible look-up table registers not accessible lcd outputs are forced low table 13-3 hardware power save mode summary host interface not accessible memory read/write not accessible look-up table registers not accessible lcd outputs are forced low table 13-4 power save mode function summary hardware power save software power save normal io access possible? no yes yes memory access possible? no yes yes look-up table registers access possible? no no yes sequence controller running? no no yes display active? no no yes lcdpwr inactive inactive active fpdat[11:0], fpshift (see note) forced low forced low active fpline, fpframe, drdy forced low forced low active 13: power save modes 1-70 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 13.4 panel power up/down sequence after chip reset or when entering/exiting a power save mode, the panel interface signals follow a power on/off sequence shown below. this sequence is essential to prevent damage to the lcd panel. figure 13-1 panel on/off sequence after chip reset, lcdpwr is inactive and the rest of the panel interface output signals are held ?ow? software initializes the chip (i.e. programs all registers except the look-up table registers) and then programs reg[03h] bits [1:0] to 11b. this starts the power-up sequence as shown. the power-up/power-down sequence delay is 127 frames. the look-up table registers may be programmed any time after reg[03h] bits[1:0] = 11b. the power-up/power-down sequence also occurs when exiting/entering software power save mode. 13.5 turning off bclk between accesses bclk may be turned off (held low) between accesses if the following rules are observed: 1. bclk must be turned off/on in a glitch free manner 2. bclk must continue for a period equal to [8t bclk + 12t mclk ] after the end of the access (rdy# asserted or wait# deasserted). 3. bclk must be present for at least one t bclk before the start of an access. reset# lcdpwr panel interface output signals (except lcdpwr) 0 frame 127 frames 0 frame power save mode power-down power-up power-up software power save 00 11 00 11 hardware power save reg[03h] bits [1:0] or 13: power save modes s1d13705f00a hardware functional epson 1-71 specification (x27a-a-001-06) 13.6 clock requirements the following table shows what clock is required for which function in the s1d13705. table 13-5 s1d13705 internal clock requirements function bclk clki register read/write is required during register accesses. bclk can be shut down between accesses: allow eight bclk pulses plus 12 mclk pulses (8t bclk + 12t mclk ) after the last access before shutting bclk off. allow one bclk pulse after starting up bclk before the next access. not required memory read/write is required during memory accesses. bclk can be shut down between accesses: allow eight bclk pulses plus 12 mclk pulses (8t bclk + 12t mclk ) after the last access before shutting bclk off. allow one bclk pulse after starting up bclk before the next access. requied look-up table register read/write is required during lut register accesses. bclk can be shut down between accesses: allow eight bclk pulses plus 12 mclk pulses (8t bclk + 12 t mclk ) after the last access before shutting bclk off. allow one bclk pulse after starting up bclk before the next access. not required software power save required can be stopped after 128 frames from entering software power save, i.e. after reg[03h] bits 1-0 = 11. hardware power save not required can be stopped after 128 frames from entering hardware power save. 14: mechanical data 1-72 epson s1d13705f00a hardware functional specification (x27a-a-001-06) 14 m echanical d ata figure 14-1 mechanical drawing qfp14 qfp14 - 80 pin unit: mm 120 60 41 40 21 61 80 index 0~10? 12.0 ?0.1 12.0 ?0.1 14.0 ?0.4 14.0 ?0.4 0.5 0.18 1.4 ?0.1 0.125 1.0 0.5 ?0.2 0.1 - 0.05 + 0.1 - 0.025 + 0.05 s1d13705f00a embedded memory lcd controller programming notes and examples contents s1d13705f00a programming notes epson 2-i and examples contents 1i ntroduction .........................................................................................................................2-1 2i nitialization ..........................................................................................................................2-2 2.1 display buffer location ..................................................................................................... ............2-2 2.2 register values ............................................................................................................. ................2-2 2.3 frame rate calculation...................................................................................................... ...........2-3 3m emory m odels ....................................................................................................................2-5 3.1 1 bit-per-pixel (2 colors/gray shades)...................................................................................... ...2-5 3.2 2 bit-per-pixel (4 colors/gray shades)...................................................................................... ...2-5 3.3 4 bit-per-pixel (16 colors/gray shades)..................................................................................... ..2-6 3.4 eight bit-per-pixel (256 colors)............................................................................................ .........2-6 4l ook -u p t able (lut) ...........................................................................................................2-7 4.1 look-up table registers..................................................................................................... ..........2-8 4.2 look-up table organization .................................................................................................. .......2-8 color modes.................................................................................................................... ...........2-8 gray shade modes ............................................................................................................... ...2-12 5a dvanced t echniques .........................................................................................................2-15 5.1 virtual display ............................................................................................................. ................2-15 registers ...................................................................................................................... ............2-15 examples ....................................................................................................................... ..........2-16 5.2 panning and scrolling ....................................................................................................... ..........2-16 registers .................................................................................................................... ............2-17 examples ....................................................................................................................... ..........2-18 5.3 split screen ................................................................................................................ .................2-20 registers ...................................................................................................................... ............2-20 examples ....................................................................................................................... ..........2-22 6 lcd p ower s equencing and p ower s ave m odes ..............................................................2-23 6.1 lcd power sequencing ........................................................................................................ ......2-23 6.2 registers ................................................................................................................... ..................2-23 6.3 lcd enable/disable .......................................................................................................... ..........2-24 7h ardware r otation ............................................................................................................2-25 7.1 introduction to hardware rotation ........................................................................................... ..2-25 7.2 default portrait mode ....................................................................................................... ...........2-25 7.3 alternate portrait mode ..................................................................................................... ..........2-26 7.4 registers ................................................................................................................... ..................2-27 7.5 limitations ................................................................................................................. ..................2-28 7.6 examples.................................................................................................................... .................2-28 8i dentifying the s1d13705 ..................................................................................................2-31 9h ardware a bstraction l ayer (hal).................................................................................2-32 9.1 introduction................................................................................................................ ..................2-32 9.2 contents of the hal_struct .................................................................................................. .2-32 9.3 using the hal library ....................................................................................................... ...........2-32 9.4 api for 13705hal ............................................................................................................ ...........2-33 initialization ................................................................................................................. .............2-34 general hal support............................................................................................................ ...2-35 advanced hal functions ........................................................................................................2 -37 register / memory access ....................................................................................................... 2-40 power save..................................................................................................................... .........2-41 drawing ........................................................................................................................ ............2-42 lut manipulation ............................................................................................................... ......2-43 9.5 porting libse to a new target platform ...................................................................................... .2-44 building the libse library for sh3 target example ..................................................................2-44 contents 2-ii epson s1d13705f00a programming notes and examples building the hal library for the target example ....................................................................... 2-45 10 s ample c ode .......................................................................................................................2-46 10.1 sample code using the s1d13705 hal api............................................................................... 2-46 10.2 sample code without using the s1d13705 hal api .................................................................. 2-48 10.3 header files............................................................................................................... ................. 2-54 contents s1d13705f00a programming notes epson 2-iii and examples list of figures figure 3-1 pixel storage for 1 bpp (2 colors/gray shades) in one byte of display buffer ..................2-5 figure 3-2 pixel storage for 2 bpp (4 colors/gray shades) in one byte of display buffer ..................2-5 figure 3-3 pixel storage for 4 bpp (16 colors/gray shades) in one byte of display buffer ................2-6 figure 3-4 pixel storage for 8 bpp (256 colors) in one byte of display buffer ....................................2-6 figure 5-1 viewport inside a virtual display.................................................................................... ....2-15 figure 5-2 320 240 single panel for split screen .............................................................................2-20 figure 7-1 relationship between the default mode screen image and the image refreshed by s1d13705 ....................................................................................................................... ...2-25 figure 7-2 relationship between the alternate mode screen image and the image refreshed by s1d13705 ....................................................................................................................... ...2-26 list of tables table 2-1 s1d13705 initialization sequence ...................................................................................... .2-3 table 4-1 recommended lut values for 1 bpp color mode ..............................................................2-8 table 4-2 example lut values for 2 bpp color mode ........................................................................2-9 table 4-3 suggested lut values to simulate vga default 16 color palette....................................2-10 table 4-4 suggested lut values to simulate vga default 256 color palette..................................2-11 table 4-5 recommended lut values for 1 bpp gray shade ...........................................................2-12 table 4-6 suggested values for 2 bpp gray shade ..........................................................................2-13 table 4-7 suggested lut values for 4 bpp gray shade...................................................................2-14 table 5-1 number of pixels panned using start address..................................................................2-17 table 7-1 default and alternate portrait mode comparison...............................................................2-28 table 9-1 hal functions......................................................................................................... ...........2-33 1: introduction s1d13705f00a programming notes epson 2-1 and examples (x27a-g-002-01) 1i ntroduction this guide demonstrates how to program the s1d13705 embedded memory color lcd controller. the guide presents the basic concepts of the lcd controller and provides methods to directly program the registers. it explains some of the advanced techniques used and the special features of the s1d13705. the guide also introduces the hardware abstraction layer (hal), which is designed to make programming the s1d13705 as easy as possible. future s1d1370x products will support the hal allowing oems the ability to upgrade to future chips with relative ease. 2: initialization 2-2 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 2i nitialization prior to doing anything else with the s1d13705 the controller must be initialized. initialization is the process of setting up the control registers to a known state in order to generate proper display signals. 2.1 display buffer location before we can perform the initialization we have to know where to tnd the s1d13705 display memory and control registers. the s1d13705 contains 80 kilobytes of internal display memory. external support logic must be employed to decode the starting address for this display memory in cpu address space. on the s5u13705b00c pc platform evaluation boards the address is usually txed at f00000h. alternatively the address can be set to d0000h. the control registers are located by adding 1ffe0h (128 kb less 32 bytes) to the base memory address. thus, on the typical pc platform, we access control register 0 at address f1ffe0h. control register 5 would be located at address f1ffe5, etc. 2.2 register values this section describes the register settings and sequence of setting the registers. in addition to these setting the look-up table must be programmed with appropriate colors. look-up table setup is not covered here. see section 4 on page 2-7 of this manual for look-up table programming details. the following initialization, presented in table form, shows the sequences and values to set the registers. the notes column comments the reason for the particular value being written. this example writes to all the necessary registers. initially, when the s1d13705 is powered up, all registers, unless noted otherwise in the specitcation, are set to zero. this example programs these registers to zero to establish a known state. in practice, it may be possible to write to only a subset of the registers. the example initializes a s1d13705 to control a panel with the following specitcations: 320 2: initialization s1d13705f00a programming notes epson 2-3 and examples (x27a-g-002-01) 2.3 frame rate calculation frame rate specites the number of complete frame which are drawn on the display in one second. contguring a frame rate that is too high or too low adversely effects the quality of the displayed image. system contguration imposes certain non-variable limitations. for instance the width and height of the display panel are txed as is, typically, the input clock to the s1d13705. from the following formula it is evident that the two variables the programmer can use to adjust frame rate are horizontal and vertical non-display periods. table 2-1 s1d13705 initialization sequence register value (hex) notes see also [01] 0010 0011 (23) select a passive, single, color panel with an 8-bit data width [02] 1100 0000 (c0) select 8-bit per pixel color depth [03] 0000 0011 (03) select normal power operation [04] 0010 0111 (27) horizontal display size = (reg[04]+1)*8 = (39+1) * 8 = 320 pixels [05] 1110 1111 (ef) vertical display size = reg[06][05] + 1 = 0000 0000 1110 1111 + 1 = 239 +1 = 240 lines [06] 0000 0000 (00) [07] 0000 0000 (00) fpline start position (only required for tft con?uration) [08] 0000 0000 (00) horizontal non-display period = (reg[08] + 4) * 8 = 4 * 8 = 32 pixels frame rate calculation [09] 0000 0000 (00) fpframe start position (only required for tft con?uration) [0a] 0000 0011 (03) vertical non-display period = reg[0a] = 3 lines frame rate calculation [0b] 0000 0000 (00) mod rate is only required by some monochrome panels [0c] 0000 0000 (00) screen 1 start address - set to 0 for initialization ?.3 split screen on page 2-20 [0d] 0000 0000 (00) [0e] 0000 0000 (00) screen 2 start address - set to 0 for initialization ?.3 split screen on page 2-20 [0f] 0000 0000 (00) [10] 0000 0000 (00) screen 1 / screen 2 start address msb - set to 0 [11] 0000 0000 (00) memory address offset - not virtual setup - so set to 0 ?.1 virtual display on page 2-15 [12] 1111 1111 (ff) set the vertical size to the maximum value. ?.3 split screen on page 2-20 [13] 0000 0011 (03) [15] leave the lut alone for now ? look-up table (lut) on page 2-7 [17] [18] 0000 0000 (00) gpio control and status registers - set to ?? [19] 0000 0000 (00) [1a] 0000 0000 (00) set the scratch pad bits to ?? [1b] 0000 0000 (00) this is not portrait mode so set this register to ?? ?.1 introduction to hard- ware rotation on page 2- 25 [1c] 0000 0000 (00) line byte count is only required for portrait mode. 2: initialization 2-4 epson s1d13705f00a programming notes and examples (x27a-g-002-01) the following are the formulae for determining the frame rate of a panel. the formula for a single passive or tft panel is calculated as follows: for a dual passive panel the formula is: where : pclk = pixel clock (in hz) hdp = horizontal display period (in pixels) hndp = horizontal non-display period (in pixels) vdp = vertical display period (in lines) vndp = vertical non-display period (in lines) in addition to varying the hndp and vndp times we can also select divider values which will reduce clki to one half, one quarter up to one eight of the clki value. the example below is a portion of a ? routine to calculate hndp and vndp from a desired frame rate. for (int loop = 0; loop < 2; loop++) { for (vndp = 2; vndp < 0x3f; vndp += 3) { // solve for hndp hndp = (pclk / (framerate * (vdp + vndp))) - hdp; if ((hndp >= 32) && (hndp <= 280)) { // solve for vndp. vndp = (pclk / (framerate * (hdp + hndp))) - vdp; // if we have satisfied vndp then we're done. if ((vndp >= 0) && (vndp <= 0x3f)) goto donecalc; } } // divide clki and try again. // (reg[02] allows us to dived clki by 2) pclk /= 2; } // if we still can't hit the frame rate - throw an error. if ((vndp < 0) || (vndp > 0x3f) || (hndp < 32) || (hndp > 280)) { sprintf("error: unable to set the desired frame rate.\n"); exit(1); } this routine trst performs a formula rearrangement so that hndp or vndp can be solved. start with vndp set to a small value. loop increasing vndp and solving the equation for hndp until satisfactory hndp and vndp values are found. if no satisfactory values are found then divide clki and repeat the process. if a satisfactory frame rate still can?t be reached - return an error. note: most passive (stn) panels are tolerant of nearly any combination of hndp and vndp values, however panel specifications generally specify only a few lines of vertical non-display period. the s1d13705 is capable of generating a vertical non-display period of up to sixty-three lines. this amount of vndp is far too great a non-display period and will likely degrade display qual- ity. similarly, setting a large hndp value may cause a degrade in image quality. if possible the system should be designed such that vndp values of 7 or less lines and hndp values of 20 or less characters can be selected. framerate pclk hdp hndp + () () () ?? ?? 3: memory models s1d13705f00a programming notes epson 2-5 and examples (x27a-g-002-01) 3m emory m odels the s1d13705 is capable of operating at four different color depths. for each color depth the data format is packed pixel. s1d13705 packed pixel modes can range from one byte containing eight adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp). packed pixel data may be envisioned as a stream of pixels. in this stream, pixels are packed in adjacent to each other. if a pixel requires four bits then it will be located in the four most signitcant bits of a byte. the pixel to the immediate right on the display will occupy the lower four bits of the same byte. the next two pixels to the immediate right are located in the following byte, etc. 3.1 1 bit-per-pixel (2 colors/gray shades) 1-bit pixels support two color/gray shades. in this memory format each byte of display buffer contains eight adjacent pixels. setting or resetting any pixel requires reading the entire byte, masking out appropriate bits and, if necessary, setting bits to 1. when using a color panel the two colors are derived by indexing into positions 0 and 1 of the look- up table. if the trst two lut elements are set to black (rgb = 0 0 0) and white (rgb = f f f) then each 0 bit of display memory will display as a black pixel and each 1 bit will display as a white pixel. the two lut entries can be set to any desired colors, for instance red and green or cyan and yellow. for monochrome panels the two displayed gray shades are generated by indexing into the trst two elements of the green component of the look-up table (lut). thus, by manipulating the green lut components we can set either of the two gray shades to any of sixteen possible levels. figure 3-1 pixel storage for 1 bpp (2 colors/gray shades) in one byte of display buffer 3.2 2 bit-per-pixel (4 colors/gray shades) 2-bit pixels support four color/gray shades. in this memory format each byte of display buffer contains four adjacent pixels. setting or resetting any pixel requires reading the entire byte, masking out the appropriate bits and, if necessary, setting bits to 1. color panels derive their four colors by indexing into positions 0 through 3 of the look-up table. these four lut entries can be set to any of the 4096 possible color combinations. monochrome panels derive four gray shades by indexing into the trst four elements of the green component of the look-up table. any of the four lut entries can be set to any of the sixteen possible gray shades. figure 3-2 pixel storage for 2 bpp (4 colors/gray shades) in one byte of display buffer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 bit 1 pixel 0 bit 0 pixel 1 bit 1 pixel 1 bit 0 pixel 2 bit 1 pixel 2 bit 0 pixel 3 bit 1 pixel 3 bit 0 3: memory models 2-6 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 3.3 4 bit-per-pixel (16 colors/gray shades) four bit pixels support 16 color/gray shades. in this memory format each byte of display buffer contains two adjacent pixels. setting or resetting any pixel requires reading the entire byte, masking out the upper or lower nibble (4 bits) and setting the appropriate bits to 1. color panels can display up to sixteen colors simultaneously. these sixteen colors are derived by indexing into the trst sixteen elements of the look-up table. each of these colors may be selected from the 4096 possible available colors. on a monochrome panel the gray shades are generated by indexing into the trst sixteen green components of the lut. each of these sixteen possible gray shades can be adjusted to any of the sixteen possible gray shades. for instance, one could program the trst eight green lut entries to be 0 and the second green lut entries to be ffh. this would result in nibble values of 0 through 7 displaying as black and nibble values 8 through 0fh displaying as white. figure 3-3 pixel storage for 4 bpp (16 colors/gray shades) in one byte of display buffer 3.4 eight bit-per-pixel (256 colors) in eight bit-per-pixel mode one byte of display buffer represents one pixel on the display. at this color depth the read-modify-write cycles, required by the lessor pixel depths, are eliminated. when using a color panel, each byte of display memory acts as and index to one element of the lut. the displayed color is arrived at by taking the display memory value as an index into the lut. eight bit per pixel is not supported for monochrome display modes. the reason is that each element of the lut supports a 4-bit (sixteen value) level for red, green and blue. in monochrome display modes on the green value is used to set the gray intensity. thus we have sixteen possible grey values but, because of the color. figure 3-4 pixel storage for 8 bpp (256 colors) in one byte of display buffer bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 bit 3 pixel 0 bit 2 pixel 0 bit 1 pixel 0 bit 0 pixel 1 bit 3 pixel 1 bit 2 pixel 1 bit 1 pixel 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 red bit 2 red bit 1 red bit 0 green bit 2 green bit 1 green bit 0 blue bit 1 blue bit 0 4: look-up table (lut) s1d13705f00a programming notes epson 2-7 and examples (x27a-g-002-01) 4l ook -u p t able (lut) this section is supplemental to the description of the look-up table architecture found in the s1d13705 hardware functional specitcation. covered here is a review of the lut registers, recommendations for the color and gray shade lut values, and additional programming considerations for the lut. refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-01 for more detail. the s1d13705 look-up table consists of 256 indexed red/green/blue entries. each entry is 4 bits wide. two registers, reg[15h] and reg[17h], control access to the lut. each look-up table entry consists of a red, green, and blue component. each component consisting of four bits, or sixteen intensity levels. any look-up table element can be selected from a palette of 4096 (16 4: look-up table (lut) 2-8 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 4.1 look-up table registers lut address the lut address register selects which of the 256 lut entries will be accessed. after three successive reads/writes to the data register this register is automatically incremented to point to the next address. lut data this register is where the 4-bit red/green/blue data value is written/read. immediately after setting the lut index with register [15h] this register accesses the red element of the look-up table. with each successive write/read the internal bank select is incremented. thus the second access is from the green element and the third is from the blue element. after the third access the lut address is incremented by one, then next access to this register will be the red element of the next look-up table index. 4.2 look-up table organization color modes 1 bpp color when the s1d13705 is con?ured for 1 bpp color mode, the lut is limited to selecting colors from the ?st two entries. the two lut entries can be any two rgb values but are typically set to black- and-white. each byte in the display buffer contains eight adjacent pixels. if a bit has a value of ??then the color in lut 0 index is displayed. a bit value of ??results in the color in lut 1 index being displayed. the following table shows the recommended values for obtaining a black-and-white mode while in 1 bpp on a color panel. reg[15h] look-up table address registe read/write lut address bit 7 lut address bit 6 lut address bit 5 lut address bit 4 lut address bit 3 lut address bit 2 lut address bit 1 lut address bit 0 reg[17h] look-up table data register read/write lut data bit 3 lut data bit 2 lut data bit 1 lut data bit 0 n/a n/a n/a n/a table 4-1 recommended lut values for 1 bpp color mode index red green blue 00 00 00 00 01 f0 f0 f0 02 00 00 00 ... 00 00 00 ff 00 00 00 unused entries 4: look-up table (lut) s1d13705f00a programming notes epson 2-9 and examples (x27a-g-002-01) 2 bpp color when the s1d13705 is con?ured for 2 bpp color mode, the displayed colors are selected from the ?st four entries of the look-up table. the lut entries may be set to any of the 4096 possible colors. each byte in the display buffer contains four adjacent pixels. if a bit combination has a value of ?0? then the color in lut index 0 is displayed. a bit value of ?1?results in the color in lut index 1 being displayed. likewise the bit combination of ?0?displays from the third lut entry and ?1? displays a color from the fourth lut entry. the following table shows the example values for 2 bit-per-pixel display mode. table 4-2 example lut values for 2 bpp color mode index red green blue 00 00 00 00 01 70 70 70 02 a0 a0 a0 03 f0 f0 f0 04 00 00 00 ... 00 00 00 ff 00 00 00 indicates unused entries 4: look-up table (lut) 2-10 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 4 bpp color when the s1d13705 is con?ured for 4 bpp color mode, the displayed colors are selected from the ?st sixteen entries of the look-up table. the lut entries may be set to any of the 4096 possible colors. each byte in the display buffer contains two adjacent pixels. if a nibble has a value of ?000?then the color in lut index 0 is displayed. a nibble value of ?001?results in the color in lut index 1 being displayed. the pattern continues to the nibble pattern of ?111?which results in the sixteenth color of the look-up table being displayed. the following table shows the example values for 4 bit-per-pixel display mode. these colors simulate the colors used by the sixteen color modes of a vga. table 4-3 suggested lut values to simulate vga default 16 color palette index red green blue 00 00 00 00 01 00 00 a0 02 00 a0 00 03 00 a0 a0 04 a0 00 00 05 a0 00 a0 06 a0 a0 00 07 a0 a0 a0 08 00 00 00 09 00 00 f0 0a 00 f0 00 0b 00 f0 f0 0c f0 00 00 0d f0 00 f0 0e f0 f0 00 0f f0 f0 f0 10 00 00 00 ... 00 00 00 ff 00 00 00 indicates unused entries 4: look-up table (lut) s1d13705f00a programming notes epson 2-11 and examples (x27a-g-002-01) 8 bpp color when the s1d13705 is con?ured for 8 bpp color mode the entire look-up table is used to display images. each of the lut entries may be set to any of the 4096 possible colors. each byte in the display buffer represents one pixels. the byte value is used directly as an index into one of the 256 lut entries. a display memory byte with a value of 00h will display the color contained in the ?st look-up table entry while a display memory byte of ffh will display a color formed byte the two hundred and ?ty sixth look-up table entry. the following table depicts lut values which approximate the vga default 256 color palette. table 4-4 suggested lut values to simulate vga default 256 color palette index r g b index r g b index r g b index r g b 00 00 00 00 40 f0 70 70 80 30 30 70 c0 00 40 00 01 00 00 a0 41 f0 90 70 81 40 30 70 c1 00 40 10 02 00 a0 00 42 f0 b0 70 82 50 30 70 c2 00 40 20 03 00 a0 a0 43 f0 d0 70 83 60 30 70 c3 00 40 30 04 a0 00 00 44 f0 f0 70 84 70 30 70 c4 00 40 40 05 a0 00 a0 45 d0 f0 70 85 70 30 60 c5 00 30 40 06 a0 50 00 46 b0 f0 70 86 70 30 50 c6 00 20 40 07 a0 a0 a0 47 90 f0 70 87 70 30 40 c7 00 10 40 08 50 50 50 48 70 f0 70 88 70 30 30 c8 20 20 40 09 50 50 f0 49 70 f0 90 89 70 40 30 c9 20 20 40 0a 50 f0 50 4a 70 f0 b0 8a 70 50 30 ca 30 20 40 0b 50 f0 f0 4b 70 f0 d0 8b 70 60 30 cb 30 20 40 0c f0 50 50 4c 70 f0 f0 8c 70 70 30 cc 40 20 40 0d f0 50 f0 4d 70 d0 f0 8d 60 70 30 cd 40 20 30 0e f0 f0 50 4e 70 b0 f0 8e 50 70 30 ce 40 20 30 0f f0 f0 f0 4f 70 90 f0 8f 40 70 30 cf 40 20 20 10 00 00 00 50 b0 b0 f0 90 30 70 30 d0 40 20 20 11 10 10 10 51 c0 b0 f0 91 30 70 40 d1 40 20 20 12 20 20 20 52 d0 b0 f0 92 30 70 50 d2 40 30 20 13 20 20 20 53 e0 b0 f0 93 30 70 60 d3 40 30 20 14 30 30 30 54 f0 b0 f0 94 30 70 70 d4 40 40 20 15 40 40 40 55 f0 b0 e0 95 30 60 70 d5 30 40 20 16 50 50 50 56 f0 b0 d0 96 30 50 70 d6 30 40 20 17 60 60 60 57 f0 b0 c0 97 30 40 70 d7 20 40 20 18 70 70 70 58 f0 b0 b0 98 50 50 70 d8 20 40 20 19 80 80 80 59 f0 c0 b0 99 50 50 70 d9 20 40 20 1a 90 90 90 5a f0 d0 b0 9a 60 50 70 da 20 40 30 1b a0 a0 a0 5b f0 e0 b0 9b 60 50 70 db 20 40 30 1c b0 b0 b0 5c f0 f0 b0 9c 70 50 70 dc 20 40 40 1d c0 c0 c0 5d e0 f0 b0 9d 70 50 60 dd 20 30 40 1e e0 e0 e0 5e d0 f0 b0 9e 70 50 60 de 20 30 40 1f f0 f0 f0 5f c0 f0 b0 9f 70 50 50 df 20 20 40 20 00 00 f0 60 b0 f0 b0 a0 70 50 50 e0 20 20 40 21 40 00 f0 61 b0 f0 c0 a1 70 50 50 e1 30 20 40 22 70 00 f0 62 b0 f0 d0 a2 70 60 50 e2 30 20 40 23 b0 00 f0 63 b0 f0 e0 a3 70 60 50 e3 30 20 40 24 f0 00 f0 64 b0 f0 f0 a4 70 70 50 e4 40 20 40 25 f0 00 b0 65 b0 e0 f0 a5 60 70 50 e5 40 20 30 26 f0 00 70 66 b0 d0 f0 a6 60 70 50 e6 40 20 30 27 f0 00 40 67 b0 c0 f0 a7 50 70 50 e7 40 20 30 28 f0 00 00 68 00 00 70 a8 50 70 50 e8 40 20 20 29 f0 40 00 69 10 00 70 a9 50 70 50 e9 40 30 20 2a f0 70 00 6a 30 00 70 aa 50 70 60 ea 40 30 20 2b f0 b0 00 6b 50 00 70 ab 50 70 60 eb 40 30 20 2c f0 f0 00 6c 70 00 70 ac 50 70 70 ec 40 40 20 4: look-up table (lut) 2-12 epson s1d13705f00a programming notes and examples (x27a-g-002-01) gray shade modes gray shade modes are monochrome display modes. monochrome display modes use the look-up table in a very similar fashion to the color modes. this most signitcant difference is that the monochrome display modes use only the intensity of the green element of the look-up table to form the gray level. one side effect of using only green for intensity selection is that in gray shade modes there are only sixteen possible intensities. 8 bit-per-pixel is not supported for gray shade modes. 1 bpp gray shade when the s1d13705 is con?ured for 1 bpp gray shade mode, the lut is limited to selecting colors from the ?st two green entries. the two lut entries can be set to any of sixteen possible intensities. typically they would be set to 0h (black) and fh (white). each byte in the display buffer contains eight adjacent pixels. if a bit has a value of ??then the color in the green lut 0 index is displayed. a bit value of ??results in the color in green lut 1 index being displayed. the following table shows the recommended values 1 bpp gray shade display mode 2d b0 f0 00 6d 70 00 50 ad 50 60 70 ed 30 40 20 2e 70 f0 00 6e 70 00 30 ae 50 60 70 ee 30 40 20 2f 40 f0 00 6f 70 00 10 af 50 50 70 ef 30 40 20 30 00 f0 00 70 70 00 00 b0 00 00 40 f0 20 40 20 31 00 f0 40 71 70 10 00 b1 10 00 40 f1 20 40 30 32 00 f0 70 72 70 30 00 b2 20 00 40 f2 20 40 30 33 00 f0 b0 73 70 50 00 b3 30 00 40 f3 20 40 30 34 00 f0 f0 74 70 70 00 b4 40 00 40 f4 20 40 40 35 00 b0 f0 75 50 70 00 b5 40 00 30 f5 20 30 40 36 00 70 f0 76 30 70 00 b6 40 00 20 f6 20 30 40 37 00 40 f0 77 10 70 00 b7 40 00 10 f7 20 30 40 38 70 70 f0 78 00 70 00 b8 40 00 00 f8 00 00 00 39 90 70 f0 79 00 70 10 b9 40 10 00 f9 00 00 00 3a b0 70 f0 7a 00 70 30 ba 40 20 00 fa 00 00 00 3b d0 70 f0 7b 00 70 50 bb 40 30 00 fb 00 00 00 3c f0 70 f0 7c 00 70 70 bc 40 40 00 fc 00 00 00 3d f0 70 d0 7d 00 50 70 bd 30 40 00 fd 00 00 00 3e f0 70 b0 7e 00 30 70 be 20 40 00 fe 00 00 00 3f f0 70 90 7f 00 10 70 bf 10 40 00 ff 00 00 00 table 4-5 recommended lut values for 1 bpp gray shade address red green blue 00 00 00 00 01 00 f0 00 02 00 00 00 ... 00 00 00 ff 00 00 00 unused entries table 4-4 suggested lut values to simulate vga default 256 color palette (continued) index r g b index r g b index r g b index r g b 4: look-up table (lut) s1d13705f00a programming notes epson 2-13 and examples (x27a-g-002-01) 2 bpp gray shade when the s1d13705 is con?ured for 2 bpp gray shade, the displayed colors are selected from the ?st four green entries in the look-up table. the remaining entries of the lut are unused. each of the four entries can be set to any of the sixteen possible colors. each byte in the display buffer contains four adjacent pixels. if a bit combination has a value of ?0? then the intensity in the green lut index 0 is displayed. a bit value of ?1?results in the intensity represented by the green in lut index 1 being displayed. likewise the bit combination of ?0? displays from the third lut entry and ?1?displays a from the fourth lut entry. the following table shows the example values for 2 bit-per-pixel display mode. table 4-6 suggested values for 2 bpp gray shade index red green blue 0 00 00 00 1 00 50 00 2 00 a0 00 3 00 f0 00 4 00 00 00 ... 00 00 00 ff 00 00 00 indicates unused entries 4: look-up table (lut) 2-14 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 4 bpp gray shade when the s1d13705 is con?ured for 4 bpp gray shade mode the displayed colors are selected from the green values of the ?st sixteen entries of the look-up table. each of the sixteen entries can be set to any of the sixteen possible intensity levels. each byte in the display buffer contains two adjacent pixels. if a nibble pattern is ?000?then the green intensity of lut index 0 is displayed. a nibble value of ?001?results in the green intensity in lut index 1 being displayed. the pattern continues to the nibble pattern of ?111?which results in the sixteenth intensity of look-up table being displayed. the following table shows the example values for 4 bit-per-pixel display mode. table 4-7 suggested lut values for 4 bpp gray shade index red green blue 00 00 00 00 01 00 10 00 02 00 20 00 03 00 30 00 04 00 40 00 05 00 50 00 06 00 60 00 07 00 70 00 08 00 80 00 09 00 90 00 0a 00 a0 00 0b 00 b0 00 0c 00 c0 00 0d 00 d0 00 0e 00 e0 00 0f 00 f0 00 10 00 00 00 ... 00 00 00 ff 00 00 00 indicates unused entries 5: advanced techniques s1d13705f00a programming notes epson 2-15 and examples (x27a-g-002-01) 5a dvanced t echniques this section contains programming suggestions for the following: virtual display panning and scrolling split screen display 5.1 virtual display virtual display refers to the situation where the image to be viewed is larger than the physical display. the difference can be in the horizontal, vertical or both dimensions. to view the image, the display is used as a window into the display buffer. at any given time only a portion of the image is visible. panning and scrolling are used to view the full image. the memory address offset register determines the number of horizontal pixels in the virtual image. the offset register can be used to specify from 0 to 255 additional words for each scan line. at 1 bpp, 255 words span an additional 4,080 pixels. at 8 bpp, 255 words span an additional 510 pixels. the maximum vertical size of the virtual image is the result of dividing 81920 bytes of display memory by the number of bytes on each line (i.e. at 1 bpp with a 320 figure 5-1 viewport inside a virtual display registers memory address offset register reg[11h] forms an 8-bit value called the memory address offset. this offset is the number of additional words on each line of the display. if the offset is set to zero there is no virtual width. this value does not represent the number of words to be shown on the display. the display width is set in the horizontal display width register. note: this value does not represent the number of words to be shown on the display. the display width is set in the horizontal display width register. reg[11h] memory address offset register memory address offset bit 7 memory address offset bit 6 memory address offset bit 5 memory address offset bit 4 memory address offset bit 3 memory address offset bit 2 memory address offset bit 1 memory address offset bit 0 320 240 viewport 640 480 ?irtual?display 5: advanced techniques 2-16 epson s1d13705f00a programming notes and examples (x27a-g-002-01) examples example 1 in this example we go through the calculations to display a 640 480 image on a 320 240 panel at 2 bpp. step 1: calculate the number of pixels per word for this color depth. at 2 bpp each byte is comprised of 4 pixels, therefore each word contains 8 pixels. pixels_per_word = 16 / bpp = 16 / 2 = 8 step 2: calculate the memory address offset register value we require a total of 640 pixels. the horizontal display register will account for 320 pixels, this leaves 320 pixels for the memory address offset register to account for. offset = pixels / pixels_per_word = 320 / 8 = 40 = 28h the memory address offset register, reg[11h], will have to be set to 28h to satisfy the above condition. example 2 from the above, what is the maximum number of lines our image can contain? step 1: calculate the number of bytes on each line. bytes_per_line = pixels_per_line / pixels_per_byte = 640 / 4 = 160 each line of the display requires 160 bytes. step 2: calculate the number of lines the s1d13705 is capable of. total_lines = memory / bytes_per_line = 81920 / 160 = 512 we can display a maximum of 512 lines. our example image requires 480 lines so this example can be done. 5.2 panning and scrolling panning and scrolling describe the operation of moving a physical display viewport about a virtual image in order to view the entire image a portion at time. for example, after setting up the previous example (virtual display) and drawing an image into it we would only be able to view one quarter of the image. panning and scrolling are used to reveal the rest of the image. panning describes the horizontal (side to side) motion of the viewport. when panning to the right the image in the viewport appears to slide to the left. when panning to the left the image to appears to slide to the right. scrolling describes the vertical (up and down) motion of the viewport. scrolling down causes the image to appear to slide up and scrolling up causes the image to appear to slide down. both panning and scrolling are performed by modifying the start address register. the start address registers in the s1d13705 are a word offset to the data to be displayed in the top left corner of a frame. changing the start address by one means a change on the display of the number of pixels in one word. the number of pixels in word varies according to the color depth. at 1 bit-per-pixel a word contains sixteen pixels. at 2 bit-per-pixel there are eight pixels, at 4 bit-per-pixel there are four pixels and at 8 bit-per-pixel there is two pixels in each word. the number of pixels in each word represent the tnest step we can pan to the left or right. when portrait mode (see ? hardware rotation on page 2-25) is enabled the start address registers become offsets to bytes. in this mode the step rate for the start address registers if halved making for smoother panning. 5: advanced techniques s1d13705f00a programming notes epson 2-17 and examples (x27a-g-002-01) registers screen 1 start address registers these three registers form the seventeen bit screen 1 start address. screen 1 is displayed starting at the top left corner of the display. in landscape mode these registers form the word offset to the ?st byte in display memory to be displayed in the upper left corner of the screen. changing these registers by one will shift the display image 2 to 16 pixels, depending on the current color depth. in portrait mode these registers form the offset to the display memory byte where screen 1 will start displaying. changing these registers in portrait mode will result in a shift of 1 to 8 pixels depending on the color depth. refer to table 5-1 to see the minimum number of pixels affected by a change of one to these registers reg[0ch] screen 1 display start address 0 (lsb) start addr bit 7 start addr bit 6 start addr bit 5 start addr bit 4 start addr bit 3 start addr bit 2 start addr bit 1 start addr bit 0 reg[0dh] screen 1 display start address 1 (msb) start addr bit 15 start addr bit 14 start addr bit 13 start addr bit 12 start addr bit 11 start addr bit 10 start addr bit 9 start addr bit 8 reg[10h] screen 1 display start address 2 (msb) n/a n/a n/a n/a n/a n/a n/a start addr bit 16 table 5-1 number of pixels panned using start address color depth (bpp) pixels per word landscape mode number of pixels panned pixels per byte portrait mode number of pixels panned 116 16 8 8 28 8 4 4 44 4 2 2 82 2 1 1 5: advanced techniques 2-18 epson s1d13705f00a programming notes and examples (x27a-g-002-01) examples for the following examples we base our calculations on a 4 bit-per-pixel image displayed on a 256w ?nitialization? on page 2-2 and section 5.1, ?irtual display? on page 2-15 for assistance with these settings. these examples are shown using a c-like syntax. example 3 panning (right and left) to pan to the right increase the start address value by one. to pan to the left decrease the start address value. keep in mind that, with the exception of 8 bit-per-pixel portrait display mode, the display will jump by more than one pixel as a result of changing the start address registers. panning to the right. startword = getstartaddress(); startword ++; setstartaddress(startword); panning to the left. startword = getstartaddress(); startword --; if (startword < 0) startword = 0; setstartaddress(startword); the routine getstartaddress() is one which will read the start address registers and return the start address as a long value. it would be written similar to: long getstartaddress() { return ((reg[10] & 1) * 65536) + (reg[0d] * 256) + (reg[0c]); } the routine setstartaddress() break up its long integer argument into three register values and store the values. void setstartaddress(long sa) { reg[0c] = sa & 0xff; reg[0d] = (sa >> 8) & 0xff; reg[10] = (sa >> 16) & 0xff; } 5: advanced techniques s1d13705f00a programming notes epson 2-19 and examples (x27a-g-002-01) example 4 scrolling (up and down) to scroll down, increase the value in the screen 1 display start address register by the number of words in one virtual scan line. to scroll up, decrease the value in the screen 1 display start address register by the number of words in one virtual scan line. a virtual scan line includes both the number of bytes required by the physical display and any extra bytes that may be being used for creating a virtual width on the display. the previous dimensions are still in effect for this example (i.e. 320w startword = getstartaddress(); startword -= words_per_line; if (startword < 0) startword = 0; setstartaddress(startword); to scroll down. startword = getstartaddress(); startword += words_per_line; setstartaddress(startword); } 5: advanced techniques 2-20 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 5.3 split screen occasionally the need arises to display two different but related images. take, for example, a game where the main play area requires rapid updates and game status, displayed at the bottom of the screen, requires infrequent updates. the split screen feature of the s1d13705 allows a programmer to setup a display in such a manor. when correctly contgured the programmer has only to update the main area on a regular basis. occasionally, as the need arises, the secondary area is updated. the tgure below illustrates how a 320 figure 5-2 320 240 single panel for split screen in split screen operation ?mage 1" is taken from the display memory location pointed to by the screen 1 start address registers and is always located at the top of the screen. ?mage 2" is taken from the display memory location pointed to by the screen 2 start address registers. the line where ?mage 1" end and ?mage 2" begins is determined by the screen 1 vertical size register. registers split screen operation is performed primarily by manipulating three register sets. screen 1 start address and screen 2 start address determine from where in display memory the trst and second images will be taken from. the vertical size registers determine how many lines screen 1 will use. the following is a description of the registers used to do split screen. screen 1 vertical size these two registers form a ten bit value which determines the size of screen 1. when the vertical size is equal to or greater than the physical number of lines being displayed there is no visible effect on the display. when the vertical size value is less than the number of physical display lines, operation is like this: 1. from the beginning of a frame to the number of lines indicated by vertical size the display data will come from the memory area pointed to by the screen 1 display start address. 2. after vertical size lines have been displayed the system will begin displaying data from the memory area pointed to by screen 2 display start address. scan line 0 image 1 ... scan line 199 scan line 200 image 2 ... scan line 239 screen 1 vertical size registers = 199 lines reg[13] screen 1 vertical size (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg[14] screen 1 vertical size (msb) n/a n/a n/a n/a n/a n/a bit 9 bit 8 5: advanced techniques s1d13705f00a programming notes epson 2-21 and examples (x27a-g-002-01) on thing that must be pointed out here is that screen 1 memory is always displayed at the top of the screen followed by screen 2 memory. this relationship holds true regardless of where in display memory screen 1 start address and screen 2 start address are pointing. for instance, screen 2 start address may point to offset zero of display memory while screen 1 start address points to a location several thousand bytes higher. screen 1 will still be shown trst on the display. while not particularly useful, it is even possible to set screen 1 and screen 2 to the same address. screen 2 start address registers these two registers form the sixteen bit screen 2 start address. screen 2 is always displayed immediately following the screen 1 data and will begin at the left-most pixel on a line. keep in mind that if the screen 1 vertical size is equal to or greater than the physical display then screen 2 will not be shown. in landscape mode these registers form the word offset to the ?st byte in display memory to be displayed. changing these registers by one will shift the display image 2 to 16 pixels, depending on the current color depth. the s1d13705 does not support split screen operation in portrait mode. screen 2 will never be used if portrait mode is selected. refer to table 5-1 to see the minimum number of pixels affected by a change of one to these registers screen 1 start address registers, reg[0c], reg[0d] and reg[10] are discussed in ?ection? on page 2-17. reg[0eh] screen 2 display start address 0 (lsb) start addr bit 7 start addr bit 6 start addr bit 5 start addr bit 4 start addr bit 3 start addr bit 2 start addr bit 1 start addr bit 0 reg[0fh] screen 2 display start address 1 (msb) start addr bit 15 start addr bit 14 start addr bit 13 start addr bit 12 start addr bit 11 start addr bit 10 start addr bit 9 start addr bit 8 5: advanced techniques 2-22 epson s1d13705f00a programming notes and examples (x27a-g-002-01) examples example 5 display 200 scanlines of image 1 and 40 scanlines of image 2. image 2 is located ?st (offset 0) in the display buffer followed immediately by image 1. assume a 320 240 display and a color depth of 4 bpp. 1. calculate the scre en 1vertical size register values. vertical_size = 200 = c8h write the vertical size lsb, reg[13h], with c8h and vertical size msb, reg[14h], with a 00h. 2. calculate the screen 1 start word address register values. screen 2 is located ?st in display memory, therefore we must calculate the number of bytes taken up by the screen 2 data. bytes_per_line = pixels_per_line / pixels_per_byte = 320 / 2 = 160 total bytes = bytes_per_line 6: lcd power sequencing and power save modes s1d13705f00a programming notes epson 2-23 and examples (x27a-g-002-01) 6 lcd p ower s equencing and p ower s ave m odes 6.1 lcd power sequencing correct power sequencing is required to prevent long term damage to lcd panels and to avoid unsightly" lines" during power-up and power-down. power sequencing allows the lcd power supply to discharge prior to shutting down the lcd logic signals. proper lcd power sequencing dictates there must be a time delay between the lcd power being disabled and the lcd signals being shut down. during power-up the lcd signals must be active prior to or when power is applied to the lcd. the time intervals vary depending on the power supply design. the s1d13705 performs automatic power sequencing in response to both software power save (reg[03h]) or in response to a hardware power save. one frame after a power save mode is set, the s1d13705 disables lcd power, and the lcd logic signals continue for one hundred and twenty seven frames allowing the lcd power supply to completely discharge. for most applications the internal power sequencing is the appropriate choice. there may be situations where the internal time delay is insuftcient to discharge the lcd power supply before the lcd signals are shut down, or the delay is too long and the designer wishes to shorten it. this section details the sequences to manually power-up and power-down the lcd interface. 6.2 registers the lcd power (lcdpwr) override bit forces lcd power inactive one frame after being toggled. as long as this bit is "1" lcd power will be disabled. the hardware power save enable bit must be set in order to activate hardware power save through gpio0. the software power save bits set and reset the software power save mode. these bits are set to "11" for normal opertion and set to "00" for power save mode. lcd logic signals to the display panel are active for 128 frames after setting either hardware or software power save modes. power sequencing overide is performed by setting the lcdpwr override bit some time before setting a power save mode for power off sequences. during power on sequences the power save mode is reset some time before the lcdpwr override is reset resulting in the lcd logic signals being active before power is applied to the panel. reg[03h] mode register 2 lcdpwr override hardware power save enable software power save bit 1 software power save bit 0 6: lcd power sequencing and power save modes 2-24 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 6.3 lcd enable/disable the descriptions below cover manually powering the lcd panel up and down. use the sequences described in this section if the power supply connected to the panel requires more than 127 frames to discharge on power-down, or if the panel requires starting the lcd logic well in advance of enabling lcd power. currently there are no known circumstances where the lcd logic must be active well in advance of lcd power. note: if 127 frame period is to long, blank the display, then reprogram the horizontal and vertical siz- es to produce a shorter frame period before using these methods. power on/enable sequence the following is a sequence for manually powering-up an lcd panel if lcd power had to be applied later than lcd logic. 1. set reg[03h] bit 3 (lcdpwr override) to ?? this ensures that lcd power will be held dis- abled. 2. enable lcd logic. this is done by either setting the gpio0 pin low to disable hardware power save mode and/or by setting reg[03h] bits 1-0 to "11" to disable software power save. 3. count ??vertical non-display periods (optional). ??corresponds the length of time lcd logic must be enabled before lcd power-up, converted to the equivalent vertical non-display periods. for example, at 72 hz counting 36 non-display periods results in a one half second delay. 4. set reg[03h] bit 3 to ??to enable lcd power. power off/disable sequence the following is a sequence for manually powering-down an lcd panel. these steps would be used if the power supply discharge requirements are larger than the default 127 frames. 1. set reg[03h] bit 3 (lcdpwr override) to ??which will disable lcd power. 2. count ??vertical non-display periods. ??corresponds to the power supply discharge time converted to the equivalent vertical non-dis- play periods. (see the previous example) 3. disable the lcd logic by setting the software power save in reg[03h] or setting hardware power save via gpio0. keep in mind that after setting the power save mode there will be 127 frames before the lcd logic signals are disabled. 7: hardware rotation s1d13705f00a programming notes epson 2-25 and examples (x27a-g-002-01) 7h ardware r otation 7.1 introduction to hardware rotation many of todays applications use the lcd panel in a swivelview orientation (typically lcd panels are landscape oriented) . in this case it becomes necessary to rotate the displayed image. this rotation can be done by software at the expense of performance or, as with the s1d13705, it can be done by hardware with no performance penalty. this discussion of display rotation is intended to augment the excellent description of the hardware functionality found in the hardware functional specitcation. the s1d13705 supports two swivelview modes: default swivelview mode and alternate swivelview mode. 7.2 default swivelview mode default swivelview mode was designed to reduce power consumption for swivelview mode use. the reduced power consumption comes with certain trade offs. the most obvious difference between the two modes is that default portrait mode requires the swivelview width be a power of two, e.g. a 240-line panel, used in swivelview mode, requires setting a virtual width of 256 pixels. also default swivelview mode is only capable of scrolling the display in two line increments. the benetts to using default swivelview mode lies in the ability to use a slower input clock and in reduced power consumption. the following tgure depicts the ways to envision memory layouts for the s1d13705 in default swivelview mode. this example uses a 320 figure 7-1 relationship between the default mode screen image and the image refreshed by s1d13705 from the programmers perspective the memory is laid out as shown on the left. the programmer accesses memory exactly as for a panel of with the dimensions of 240 256 256 image seen by programmer = image in display buffer 320 swivelview window 320 240 ab c d d c b a 240 start address swivelview window display e e image refreshed by s1d13705 start address physical memory 7: hardware rotation 2-26 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 7.3 alternate swivelview mode alternate swivelview mode does not impose the power of two line width. to rotated the image on 240 line panel requires a portrait stride of 240 pixels. alternate swivelview mode is capable of scrolling by one line at a time in response to changes to the start address registers. however, to achieve the same frame rate requires a 2 x faster input clock, therefore using more power. the following tgure depicts the ways to envision memory layouts for the s1d13705 in alternate swivelview mode. this example also uses a 480 figure 7-2 relationship between the alternate mode screen image and the image refreshed by s1d13705 from the programmers perspective the memory is laid out as shown on the left. the programmer accesses memory exactly as for a panel of with the dimensions of 480 image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 start address swivelview window display image refreshed by s1d13705 start address physical memory 7: hardware rotation s1d13705f00a programming notes epson 2-27 and examples (x27a-g-002-01) 7.4 registers this section describes the registers used to set swivelview mode operation. the screen 1 start address registers must be set correctly for swivelview mode. in swivelview mode the start address registers form a byte offset, as opposed to a word offset, into display memory. the initial required offset is the swivelview mode stride (in bytes) less one. the line byte count register informs the s1d13705 of the stride, in bytes, between two consecutive lines of display in swivelview mode. the line byte count register only affects swivelview mode operation and are ignored when the s1d13705 is in landscape display mode. the swivelview mode register contains several items for swivelview mode support. the trst is the swivelview mode enable bit. when this bit is 0 the s1d13705 is in landscape mode and the remainder of the settings in this register as well as the line byte count in reg[1ch] are ignored. set this bit to 1 to enable swivelview mode. the swivelview mode select bit selects between the default mode and the alternate mode. setting this bit to 0 selects the default swivelview mode while setting this bit to 1 enables the alternate swivelview mode. swivelview mode memory clock select is another power saving measure which can be enabled if the tnal mclk value is less than or equal to 25 mhz. memory clock select results in the s1d13705 temporarily increasing the memory clock circuitry on cpu access and resuming the slower speed when the access is complete. this results in better performance while using the least power. in swivelview display mode the clki (input clock) is routed to the swivelview section of the s1d13705 as clk. from the clk signal the mclk value can be determined from table 8-8 of the hardware functional specitcation, document number x27a-a-001-xx. if mclk is determined to be less than or equal to 25 mhz then swivelview mode memory clock select may be enabled. reg[0ch] screen 1 start word address lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg[0dh] screen 1 start word address msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reg[0eh] screen 1 start word address msb n/a n/a n/a n/a n/a n/a n/a bit 16 reg[1ch] line byte count register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg[1bh] swivelview mode register swivelview mode enable swivelview mode select n/a n/a n/a swivelview mode memory clock select swivelview mode pixel clock select bit 1 swivelview mode pixel clock select bit 0 7: hardware rotation 2-28 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 7.5 limitations the only limitation to using swivelview mode on the s1d13705 is that split screen operation is not supported. a comparison of the two swivelview modes is as follows: 7.6 examples example 6 enable default swivelview mode for a 320 240 panel at 4 bpp. before switching to swivelview mode from landscape mode, display memory should be cleared to make the user perceived transition smoother. images in display memory are not rotated automatically by hardware and a garbled image would be visible for a short period of time if video memory is not cleared. if alternate swivelview is used then the clk signal is divided in half to get the pclk signal. if the input clock divide bit, in register[02] is set we can simply reset the divider. the result of this is a pclk of exactly the same frequency as we used for landscape mode and we can use the current horizontal and vertical non-display periods. if the input clock divide bit is not set then we must recalculate the frame rate based on the a pclk value. in this example we will bypass recalculation of the horizontal and vertical non-display times (frame rate) by selecting the default swivelview mode scheme. 1. calculate and set the screen 1 start word address register. offsetbytes = (width table 7-1 default and alternate swivelview mode comparison item default swivelview mode alternate swivelview mode memory requirements the width of the rotated image must be a power of 2. in most cases, a virtual image is required where the right-hand side of the virtual image is unused and memory is wasted. for example, a 320 7: hardware rotation s1d13705f00a programming notes epson 2-29 and examples (x27a-g-002-01) linebytecount = width example 7 enable alternate swivelview mode for a 320x240 panel at 4 bpp. note: as we have to perform a frame rate calculation for this mode we need to know the following panel characteristics: 320 240 8-bit color to be run at 80 hz with a 16 mhz input clock. as in the previous example, before switching to swivelview mode, display memory should be cleared. images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared. 1. calculate and set the screen 1 start word address register. offsetbytes = (width ?.3 frame rate calculation on page 2-3 and simply ?rrive?at the following: horizontal non-display period = 88h vertical non-display period = 03h plugging the values into the frame rate calculations yields: 7: hardware rotation 2-30 epson s1d13705f00a programming notes and examples (x27a-g-002-01) for this example the horizontal non-display register [reg[08h]) needs to be set to 07h and the vertical non-display register (reg[0ah]) needs to be set to 03h. the 16,000,000/2 in the formula above represents the input clock being divided by two when this alternate swivelview mode is selected. with the values given for this example we must ensure the input clock divide bit (reg[02h] b4) is reset (with the given values it was likely set as a result of the frame rate calculations for landscape display mode). no other registers need to be altered. the display is now con?ured for swivelview mode use. offset zero of display memory corresponds to the upper left corner of the display. display memory is accessed exactly as it was for landscape mode. as this is the alternate swivelview mode the power of two stride issue encountered with the default swivelview mode is no longer an issue. the stride is the same as the swivelview mode width. in this case 120 bytes. example 8 pan the above swivelview mode image to the right by 4 pixels then scroll it up by 6 pixels. to pan by four pixels the start address needs to be advanced. 1. calculate the number of bytes to change start address by. bytes = pixels bitsperpixel / 8 = 4 4 / 8 = 2 bytes 2. increment the start address registers by the just calculated value. in this case the value write to the start address register will be 81h (7fh + 2 = 81h) to scroll by 4 lines we have to change the start address by the offset of four lines of display. 1. calculate the number of bytes to change start address by. bytesperline = linebytecount = 128 bytes = lines bytesperline = 4 128 = 512 = 200h 2. increment the start address registers by the just calculated value in this case 281h (81h + 200h) will be written to the screen 1 start address register set. set screen1 display start word address lsb (reg[0ch]) to 81h and screen1 display start word address msb (reg[0dh]) to 02h. framerate pclk hdp hndp + () vdp vndp + () ---------------------------------------------------------------------------------------- - = framerate 16 000 000 ,, 2 ----------------------------- - 320 88 + () 240 3 + () ------------------------------------------------------- 80.69 == 8: identifying the s1d13705 s1d13705f00a programming notes epson 2-31 and examples (x27a-g-002-01) 8i dentifying the s1d13705 there are several similar products in the 1350x and 1370x lcd controller families. products which can share signitcant portions of a generic code base. it may be important for a program to identify between products at run time. identitcation of the s1d13705 can be performed any time after the system has been powered up by reading reg[00h], the revision code register. the six most signitcant bits form the product identitcation code and the two least signitcant bits form the product revision. from reset (power on) the steps to identifying the s1d13705 are as follows: 1. read reg[00h]. mask off the lower two bits, the revision code, to obtain the product code. 2. the product code for the s1d13705 is 024h. 9: hardware abstraction layer (hal) 2-32 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 9h ardware a bstraction l ayer (hal) 9.1 introduction the hal is a processor independent programming library provided by epson. the hal was developed to aid the implementation of internal test programs, and provides an easy, consistent method of programming the s1d13705 on different processor platforms. the hal also allows for easier porting of programs between s1d1370x products. integral to the hal is an information structure (hal_struct) that contains contguration data on clocks, display modes, and default register values. this structure combined with the utility 1375cfg.exe allows quick customization of a program for a new target display or environment. using the hal keeps sample code simpler, although some programmers may tnd the hal functions to be limited in their scope, and may wish to program the s1d13705 without using the hal. 9.2 contents of the hal_struct the hal_struct below is contained in the tle hal.h and is required to use the hal library. typedef struct taghalstruct { char szidstring[16]; word wdetectendian; word wsize; byte regs [max_reg + 1]; dword dwclki; /* input clock frequency (in khz) */ dword dwdispmem; /* starting address of display buffer memory */ word wframerate; /* desired panel frame rate */ } hal_struct; within the regs array ia a structure which detnes all the registers described in the s1d13705 hardware functional speci?ation , document number x27a-a-001-xx. using the 1375cfg.exe utility you can adjust the content of the registers contained in hal_struct to allow for different lcd panel timing values and other default settings used by the hal. in the simplest case, the program only calls a few basic hal functions and the contents of the hal_struct are used to setup the s1d13705 for operation. 9.3 using the hal library to utilize the hal library, the programmer must include two .h tles in their code. hal.h contains the hal library function prototypes and structure detnitions, and appcfg.h contains the instance of the hal_struct that is detned in hal.h and contgured by 1375cfg.exe. for a more thorough example of using the hal see section 10.1, sample code using the s1d13705 hal api on page 2-46. note: many of the hal library functions have pointers as parameters. the programmer should be aware that little validation of these pointers is performed, so it is up to the programmer to ensure that they adhere to the interface and use valid pointers. programmers are recommended to use the highest warning levels of their compiler in order to verify the parameter types. 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-33 and examples (x27a-g-002-01) 9.4 api for 13705hal this section is a description of the hal library application programmers interface (api). updates and revisions to the hal may include new functions not included in this documentation. table 9-1 hal functions function description initialization: seregisterdevice registers the s1d13705 parameters with the hal, calls seinithal if necessary. seregisterdevice must be the ?st hal function called by an application. sesetinit programs the s1d13705 for use with the default settings, calls sesetdisplaymode to do the work, clears display memory. note: either sesetinit or sesetdisplaymode must be called after calling seregisterdevice general hal support: segetid interpret the revision code register to determine chip id segethalversion return version information on the hal library segetlastusablebyte determine the offset of the last unreserved usable byte in the display buffer segetbytesperscanline determine the number of bytes or memory consumed per scan line in current mode segetscreensize determine the height and width of the display surface in pixels sedelay use the frame rate timing to delay for required seconds (requires registers to be initialized) sesethighperformance used in color modes less than 8-bpp to toggle the high performance bit on or off advanced hal functions: sesplitinit initialize split screen variables and setup start addresses sesplitscreen set the size of either the top or bottom screen sevirtinit initialize virtual screen mode setting x and y sizes sevirtmove pan/scroll the virtual screen surface(s) hardware rotate: sesethwrotate set the hardware rotation to either portrait or landscape sesetportraitmethod call before setting hardware portrait mode to set either default or alternate portrait mode register / memory access: sesetreg write a byte value to the speci?d s1d13705 register segetreg read a byte value from the speci?d s1d13705 register sewritedisplaybytes write one or more bytes to the display buffer at the speci?d offset sewritedisplaywords write one or more words to the display buffer at the speci?d offset sewritedisplaydwords write one or more dwords to the display buffer at the speci?d offset sereaddisplaybyte read a byte from the display buffer from the speci?d offset sereaddisplayword read a word from the display buffer from the speci?d offset sereaddisplaydword read a dword from the display buffer from the speci?d offset color manipulation: sesetlut write to the look-up table (lut) entries starting at index 0 segetlut read from the lut starting at index 0 sesetlutentry write one lut entry (red, green, blue) at the speci?d index segetlutentry read one lut entry (red, green, blue) from the speci?d index sesetbitsperpixel set the color depth segetbitsperpixel determine the current color depth drawing: sesetpixel draw a pixel at (x,y) in the speci?d color segetpixel read pixel s color at (x,y) sedrawline draw a line from (x1,y1) to (x2,y2) in speci?d color sedrawrect draw a rectangle from (x1,y1) to (x2,y2) in speci?d color power save: sesetpowersavemode control s1d13705 sw power save mode (enable/disable) 9: hardware abstraction layer (hal) 2-34 epson s1d13705f00a programming notes and examples (x27a-g-002-01) initialization the following section describes the hal functions dealing with s1d13705 initialization. typically a programmer has only to concern themselves with calls to seregisterdevice() and sesetinit(). int seregisterdevice(const lphal_struc lphalinfo) description : this function registers the s1d13705 device parameters with the hal library. the device parameters include address range, register values, desired frame rate, etc., and are stored in the hal_struct structure pointed to by lphalinfo. additionally this routine allocates system memory as address space for accessing registers and the dis- play buffer. parameters: lphalinfo - pointer to hal_struct information structure return value: err_ok - operation completed with no problems err_unknown_device - the hal was unable to tnd an s1d13705. note: seregisterdevice() must be called before any other hal functions. no s1d13705 registers are changed by calling seregisterdevice(). sesetinit() description: contgures the s1d13705 for operation. this function sets all the s1d13705 control registers to their default values. initialization of the s1d13705 is a two step process to accommodate those programs (e.g. 1375play.exe) which do not initialize the s1d13705 on start-up. parameters: none return value: err_ok - operation completed with no problems note: after this call the look-up table will be set to a default state appropriate to the display type. unlike s1d1350x hal versions, this function does not call sesetdisplaymode as this function does not exist in the 13705 hal. 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-35 and examples (x27a-g-002-01) general hal support functions in this group do not tt into any specitc category of support. they provide a miscellaneous range of support for working with the s1d13705. int segetid(int * pid) description: reads the s1d13705 revision code register to determine the chip product and revi- sions. the interpreted value is returned in pid. parameters: pid - pointer to an integer which will receive the controller id. s1d13705 values returned in pid are: - id_s1d13705_rev0 - id_unknown other hal libraries will return their respective controller ids upon detection of their controller. return value: err_ok - operation completed with no problems err_unknown_device - the hal was unable to identify the display cotroller. returned when pid returnsid_unknown. void segethalversion(const char ** pversion, const char ** pstatus, const char **psta- tusrevision) description: retrieves the hal library version. the return pointers are all to ascii strings. a typical return would be: *pversion == 1.01 (hal version 1.01),*pstatus == b (the 'b' is the beta designator), *pstatusrevision == 5. the programmer need only create pointers of const char type to pass as parameters (see example below). parameters: pversion - pointer to string to return the version in. - must point to an allocated string of size ver_size pstatus - pointer to a string to return the release status in. - must point to an allocated string of size status_size pstatusrevision - pointer to return the current revision of status. - must point to an allocated string of size stat_rev_size return value: none example: const char *pversion, *pstatus, *pstatusrevision; segethalversion( &pversion, &pstatus, &pstatusrevision); 9: hardware abstraction layer (hal) 2-36 epson s1d13705f00a programming notes and examples (x27a-g-002-01) int sesetbitsperpixel(int bitsperpixel) description: this routine sets the display color depth. after performing validity checks to ensure the requested video mode can be set the appropriate registers are changed and the look-up table is set its default values appropriate to the color depth. this call is similar to a mode set call on a standard vga. parameter: bitsperpixel - desired color depth in bits per pixel. - valid arguments are: 1, 2, 4, and 8. return value: err_ok - operation completed with no problems err_failed - possible causes for this error include: 1) the desired frame rate may not be attainable with the specited input clock 2) the combination of width, height and color depth may require more memory than is available on the s1d13705. int segetbitsperpixel(int * pbitsperpixel) description: this function reads the s1d13705 registers to determine the current color depth and returns the result in pbitsperpixel . parameters: pbitsperpixel - pointer to an integer to receive current color depth. - return values will be: 1, 2, 4, or 8. return value: err_ok - operation completed with no problems int segetbytesperscanline(int * pbytes) description: determines the number of bytes per scan line of current display mode. it is assumed that the registers have already been correctly initialized before segetbytesperscan- line() is called (i.e. after initializing the hal, setting the display mode and adjusting the bits per pixel or other values). the number of bytes per scanline will include non-displayed bytes if the screen width is greater the display width, or in default swivelview mode. parameters: pbytes - pointer to an integer to receive the number of bytes per scan line return value: err_ok - operation completed with no problems int segetscreensize(int * width, int * height) description: retrieves the width and height in pixels of the display surface. the width and height are derived by reading the horizontal and vertical size registers and calculating the dimensions. virtual dimensions are not taken into account for this calculation. when the display is in swivelview mode the dimensions will be swapped. (i.e. a 640 parameters: width - pointer to an integer to receive the display width height - pointer to an integer to receive the display height return value: err_ok - the operation completed successfully 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-37 and examples (x27a-g-002-01) int sedelay(int milliseconds) description: this function will delay for the length of time specited in milliseconds before returning to the caller. this function was originally intended for non-pc platforms. information about how to access the timers was not always available however we do know frame rate and can use that for timing calculations. the s1d13705 registers must be initialized for this function to work correctly. on the pc platform this is simply a call to the c timing functions and is therefore inde- pendent of the register settings. parameters: milliseconds - time to delay in seconds return value: err_ok - operation completed with no problems err_failed - returned on non-pc platforms when the s1d13705 registers have not bee initialized int segetlastusablebyte(long * pllastbyte) description: this functions returns a pointer, as a long integer, to the last byte of usable display memory. the returned value never changes for the s1d13705. parameters: pllastbyte - pointer to a long integer to receive the offset to the last byte of display memory return value: err_ok - operation completed with no problems int sesethighperformance(bool onoff) description: this function call enables or disable the high performance bit of the s1d13705. when high performance is enabled then mclk equals pclk for all video display res- olutions. in the high performance state cpu to video memory performance is improved at the cost of higher power consumption. when high performance is disabled then mclk ranges from pclk/1 at 8 bit-per-pixel to pclk/8 at 1 bit-per-pixel. without high performance cpu to video memory speeds are slower and the s1d13705 uses less power. parameters: onoff - a boolean value (detned in hal.h) to indicate whether to enable of disable high performance. return value: err_ok- operation completed with no problems advanced hal functions advanced hal functions include the functions to support split, virtual and rotated displays. while the concept for using these features is advanced the hal makes actually using them easy. int sesetswivelviewmethod( int style ) description: this selects the swivelview mode method to be used when sesethwrotate() is called to put the s1d13705 into swivelview mode. parameters: style - call with style set to default (-1) to select default swivelview mode - call with style set to any other value to select alternate swivelview mode. 9: hardware abstraction layer (hal) 2-38 epson s1d13705f00a programming notes and examples (x27a-g-002-01) return value: err_ok - operation completed with no problems err_failed - the operation failed. int sesethwrotate(int rotate) description: this function sets the rotation scheme according to the value of 'rotate'. when por- trait mode is selected as the display rotation the scheme selected is the 'non-x2' scheme. parameters: rotate - the direction to rotate the display - valid arguments for rotate are: landscape and swivelview. return value: err_ok - operation completed with no problems err_failed - the operation failed to complete. the most likely reason for failing to set a rotate mode is an inability to set the desired frame rate when setting portrait mode. other factors which can cause a fail- ure include having a 0 hz frame rate or specifying a value other than landscape or swivelview for the rotation scheme. int sesplitinit(word scrn1addr, word scrn2addr) description: this function prepares the system for split screen operation. in order for split screen to function the starting address in the display buffer for the upper portion(screen 1) and the lower portion (screen 2) must be specited. screen 1 is always displayed above screen 2 on the display regardless of the location of their start addresses. parameters: scrn1addr - offset, in bytes, to the start of screen 1 scrn2addr - offset, in bytes, to the start of screen 2 return value: err_ok - operation completed with no problems note: it is assumed that the system has been initialized prior to calling sesplitinit(). int sesplitscreen(int screen, int visiblescanlines) description: changes the relevant registers to adjust the split screen according to the number of visible lines requested. 'whichscreen' determines which screen, 1 or 2, to base the changes on. the smallest surface screen 1 can display is one line. this is due to the way the s1d13705 operates. setting screen 1 vertical size to zero results in one line of screen 1 being displayed. the remainder of the display will be screen 2 image. parameters: screen - must be set to 1 or 2 (or use the constants screen1 or screen2) visiblescanlines- number of lines to display for the selected screen return value: err_ok - operation completed with no problems err_hal_bad_arg - argument visiblescanlines is negative or is greater than vertical panel size or whichscreen is not screen 1 or screen 2. note: changing the number of lines for one screen will also change the number of lines for the other screen. sesplitinit() must be called before calling sesplitscreen(). 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-39 and examples (x27a-g-002-01) int sevirtinit(dword virtx, dword * virty) description: this function prepares the system for virtual screen operation. the programmer passes the desired virtual width in pixels. when the routine returns virty will contain the maximum number of line that can be displayed at the requested virtual width. parameter: virtx - horizontal size of virtual display in pixels. (must be greater or equal to physical size of display) virty - pointer to an integer to receive the maximum number of displayable lines of 'virtx' width. return value: err_ok -operation completed with no problems err_hal_bad_arg - returned in three situations: 1) the virtual width (virtx) is greater than the largest possible width (virtx varies with color depth and ranges from 4096 pixels wider than the panel at 1 bit-per-pixel down to 512 pixels wider than the panel at 8 bit-per-pixel) 2) the virtual width is less than the physical width or 3) the maximum number of lines becomes less than the physical number of lines note: the system must have been initialized prior to calling sevirtinit() int sevirtmove(int screen, int x, int y) description: this routine pans and scrolls the display. in the case where split screen operation is being used, the screen argument specites which screen to move. the x and y param- eters specify, in pixels, the starting location in the virtual image for the top left cor- ner of the applicable display. parameter: screen - must be set to 1 or 2, or use the constants screen1 or screen2, to identify which screen to base calculations on x - new starting x position in pixels y - new starting y position in pixels return value: err_ok - operation completed with no problems err_hal_bad_arg - there are several reasons for this return value: 1) whichscreen is not screen1 or screen2. 2) the y argument is greater than the last available line less the screen height. note: sevirtinit() must be been called before calling sevirtmove(). 9: hardware abstraction layer (hal) 2-40 epson s1d13705f00a programming notes and examples (x27a-g-002-01) register / memory access the register/memory access functions provide access to the s1d13705 registers and display buffer through the hal. int segetreg(int index, byte * pvalue) description: reads the value in the register specited by index. parameters: index - register index to read pvalue - pointer to a byte to receive the register value. return value: err_ok - operation completed with no problems int sesetreg(int index, byte value) description: writes value specited in value to the register specited by index. parameters: index - register index to set value - value to write to the register return value: err_ok - operation completed with no problems int sereaddisplaybyte(dword offset, byte *pbyte) description: reads a byte from the display buffer at the specited offset and returns the value in pbyte. parameters: offset - offset, in bytes from start of the display buffer, to read from pbyte - pointer to a byte to return the value in return value: err_ok - operation completed with no problems err_hal_bad_arg - if the value for addr is greater 80 kb int sereaddisplayword(dword offset, word *pword) description: reads a word from the display buffer at the specited offset and returns the value in pword. parameters: offset - offset, in bytes from start of the display buffer, to read from pword - pointer to a word to return the value in return value: err_ok - operation completed with no problems. err_hal_bad_arg - if the value for addr is greater than 80 kb. int sereaddisplaydword(dword offset, dword *pdword) description: reads a dword from the display buffer at the specited offset and returns the value in pdword. parameters: offset - offset from start of the display buffer to read from pdword - pointer to a dword to return the value in return value: err_ok - operation completed with no problems. err_hal_bad_arg - if the value for addr is greater than 80 kb. 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-41 and examples (x27a-g-002-01) int sewritedisplaybytes(dword offset, byte value, dword count) description: this routine writes one or more bytes to the display buffer at the offset specited by offset. if a count greater than one is specited all bytes will have the same value. parameters: offset - offset from start of the display buffer to start writing at value - byte value to write count - number of bytes to write return value: err_ok - operation completed with no problems err_hal_bad_arg - if the value for addr or the value of addr plus count is greater than 80 kb. note: there are slight functionality differences between the s1d1370x and the s1d1350x hal. int sewritedisplaywords(dword offset, word value, dword count) description: writes one or more words to the display buffer at the offset specited by addr. if a count greater than one is specited all words will have the same value. parameters: offset - offset from start of the display buffer value - word value to write count - number of words to write return value: err_ok - operation completed with no problems err_hal_bad_arg - if the value for addr or if addr plus count is greater than 80 kb. note: there are slight functionality differences between the s1d1370x and the s1d1350x hal. int sewritedisplaydwords(dword offset, dword value, dword count) description: writes one or more dwords to the display buffer at the offset specited by addr. if a count greater than one is specited all dwordss will have the same value. parameters: offset - offset from start of the display buffer value - dword value to write count - number of dwords to write return value: err_ok - operation completed with no problems err_hal_bad_arg - if the value for addr or if addr plus count is greater than 80 kb. note: there are slight functionality differences between the s1d1370x and the s1d1350x hal. power save this section covers the hal functions dealing with the power save features of the s1d13705. int sesetpowersavemode(int pwrsavemode) description: this function sets on the s1d13705?s software selectable power save modes. parameters: pwrsavemode - integer value specifying the desired power save mode. acceptable values for pwrsavemode are: 0 - (software power save mode) in this mode registers and memory are read/writable. lcd output is forced low. 3 - (normal operation) all outputs function normally. return value: err_ok- operation completed with no problems 9: hardware abstraction layer (hal) 2-42 epson s1d13705f00a programming notes and examples (x27a-g-002-01) drawing the drawing routines cover hal functions that deal with displaying pixels, lines and shapes. int sesetpixel(long x, long y, dword color) description: draws a pixel at coordinates (x,y) in the requested color. this routine can be used for any color depth. parameters: x - horizontal coordinate of the pixel (starting from 0) y - vertical coordinate of the pixel (starting from 0) color - at 1, 2, 4, and 8 bpp color is an index into the lut. at 15 and 16 bpp color detnes the color directly (i.e. rrrrrggggggbbbbb for 16 bpp) return value: err_ok - operation completed with no problems. int segetpixel(long x, long y, dword *pcolor) description: reads the pixel color at coordinates (x,y). this routine can be used for any color depth. parameters: x - horizontal coordinate of the pixel (starting from 0) y - vertical coordinate of the pixel (starting from 0) pcolor - at 1, 2, 4, and 8 bpp pcolor points to an index into the lut. at 15 and 16 bpp pcolor points to the color directly (i.e. rrrrrggggggbbbbb for 16 bpp) return value: err_ok - operation completed with no problems. int sedrawline(int x1, int y1, int x2, int y2, dword color) description: this routine draws a line on the display from the endpoints detned by x1,y1 to the endpoint x2,y2 in the requested 'color'. currently sedrawline() only draws horizontal and vertical lines. parameters: (x1, y1)- trst endpoint of the line in pixels (x2, y2) - second endpoint of the line in pixels (see note below) color - color to draw with. 'color' is an index into the lut. return value: err_ok - operation completed with no problems note: functionality differs from the 1350x hal. int sedrawrect(long x1, long y1, long x2, long y2, dword color, bool solidfill) description: this routine draws and optionally tlls a rectangular area of display buffer. the upper right corner is detned by x1,y1 and the lower right corner is detned by x2,y2. the color, detned by color , applies both to the border and to the optional ?l. parameters: x1, y1 - top left corner of the rectangle (in pixels) x2, y2 - bottom right corner of the rectangle (in pixels) color - the color to draw the rectangle outline and tll with - color is an index into the look-up table. solidfill - flag whether to tll the rectangle or simply draw the border. - set to 0 for no tll, set to non-0 to tll the inside of the rectangle return value: err_ok - operation completed with no problems. 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-43 and examples (x27a-g-002-01) lut manipulation these functions deal with altering the color values in the look-up table. int sesetlut(byte *plut, int count) description: this routine writes one or more lut entries. the writes always start with look-up table index 0 and continue for 'count' entries. a look-up table entry consists of three bytes, one each for red, green, and blue. the color information is stored in the four most signitcant bits of each byte. parameters: plut - pointer to an array of byte lut[16][3] lut[x][0] == red component lut[x][1] == green component lut[x][2] == blue component count - the number of lut entries to write. return value: err_ok - operation completed with no problems int segetlut(byte *plut, int count) description: this routine reads one or more lut entries and puts the result in the byte array pointed to by plut. a look-up table entry consists of three bytes, one each for red, green, and blue. the color information is stored in the four most signitcant bits of each byte. parameters: plut - pointer to an array of byte lut[16][3] - plut must point to enough memory to hold 'count ' x 3 bytes of data. count - the number of lut elements to read. return value: err_ok - operation completed with no problems int sesetlutentry(int index, byte *pentry) description: this routine writes one lut entry. unlike sesetlut, the lut entry indicated by ' index' can be any value from 0 to 255. a look-up table entry consists of three bytes, one each for red, green, and blue. the color information is stored in the four most signi?ant bits of each byte. parameters: index - index to lut entry (0 to 255) plut - pointer to an array of three bytes. return value: err_ok - operation completed with no problems int segetlutentry(int index, byte *pentry) description: this routine reads one lut entry from any index. a look-up table entry consists of three bytes, one each for red, green, and blue. the color information is stored in the four most signitcant bits of each byte. parameters: index - index to lut entry (0 to 255) pentry - pointer to an array of three bytes return value: err_ok - operation completed with no problems 9: hardware abstraction layer (hal) 2-44 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 9.5 porting libse to a new target platform building epson research and development applications like a simple helloapp for a new target platform requires 3 things, the helloapp code, the 13705 hal library, and a some standard c functions (portable ones are encapsulated in our mini c library libse). components needed to build 13705 hal application for example, when building helloapp.exe for the intel 16-bit platform, you need the helloapp source tles, the 13705 hal library and its include tles, and some standard c library functions (which in this case would be supplied by the compiler as part of its run-time library). as this is a dos .exe application, you do not need to supply start-up code that sets up the chip selects or interrupts, etc... what if you wanted to build the application for an sh-3 target, one not running dos? before you can build that application to load onto the target, you need to build a c library for the target that contains enough of the standard c functions (like sprintf and strcpy) to let you build the application. epson research and development supplies the libse for this purpose, but your compiler may come with one included. you also need to build the 13705 hal library for the target. this library is the graphics chip dependent portion of the code. finally, you need to build the tnal application, linked together with the libraries described earlier. the following examples assume that you have a copy of the complete source code for the s1d13705 utilities, including the nmake maketles, as well as a copy of the gnu compiler v2.7-96q3a for hitachi sh3. these are available on the world wide web at http://www.eea.epson.com. building the libse library for sh3 target example in the libse tles, there are three main types of tles: c tles that contain the library functions. assembler tles that contain the target specitc code. maketles that describe the build process to construct the library. the c tles are generic to all platforms, although there are some customizations for targets in the form of #ifdef lcevbsh3 code (the ifdef used for the example sh3 target low cost eval board sh3). the majority of this code remains constant whichever target you build for. the assembler tles contain some platform setup code (stacks, chip selects) and jumps into the main entry point of the c code that is contained in the c tle entry.c. for our example, the assembler tle is startsh3.s and it performs only some stack setup and a jump into the code at _mainentry (entry.c). in the embedded targets, printf (in tle rprintf.c), putchar (putchar.c) and getch (kb.c) resolve to serial character input/output. for sh3, much of the detail of handling serial io is hidden in the monitor of the evaluation board, but in general the primitives are fairly straight forward, providing the ability to get characters to/from the serial port. for our target example, the nmake maketle is makesh3.mk. this maketle calls the gnu compiler at a specitc location (tooldir), enumerates the list of tles that go into the target and builds a .a library tle as the output of the build process. with nmake.exe in your path run: nmake -fmakesh3.mk helloapp source code 13705 hal library helloapp c library functions (libse for embedded platforms) 9: hardware abstraction layer (hal) s1d13705f00a programming notes epson 2-45 and examples (x27a-g-002-01) building the hal library for the target example building the hal for the target example is less complex because the code is written in c and requires little platform specitc adjustment. the nmake maketle for our example is makesh3.mk.this maketle contains the rules for building sh3 objects, the tles list for the library and the library creation rules. the gnu compiler tools are pointed to by tooldir. with nmake in your path run: nmake -fmakesh3.mk 10: sample code 2-46 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 10 s ample c ode included in the sample code section are two examples of programing the s1d13705. the trst sample uses the hal to draw a red square, wait for user input then rotates to portrait mode and draws a blue square. the second sample code performs the same procedures but directly accesses the registers of the s1d13705. these code samples are for example purposes only. 10.1 sample code using the s1d13705 hal api /* **=========================================================================== ** sample1.c - sample code demonstrating a program using the s1d13705 hal. **------------------------------------------------------------------------- ** created 1998, vancouver design centre ** copyright (c) 1998, 1999 epson research and development, inc. ** all rights reserved. **------------------------------------------------------------------------- ** ** the hal api code is configured for the following: ** ** 320x240 single color 4-bit stn ** 8 bpp - 70 hz frame rate (6 mhz clki) ** high performance enabled ** **=========================================================================== */ #include 10: sample code s1d13705f00a programming notes epson 2-47 and examples (x27a-g-002-01) { printf("\nerror: could not initialize device."); exit(1); } /* ** the default initialization cleared the display. ** draw a 100x100 red (color 1) rectangle in the upper ** left corner (0,0) of the display. */ sedrawrect(0, 0, 100, 100, 1, true); /* ** pause here. */ getch(); /* ** clear the display. do this by writing 81920 bytes */ sewritedisplaybytes(0, 0, eighty_k); /* ** setup portrait mode. */ sesethwrotate(portrait); /* ** draw a solid blue 100x100 rectangle in center of the display. ** this starting co-ordinates, assuming a 320x240 display is ** (320-100)/2 , (240-100)/2 = 110,70. */ sedrawrect(110, 70, 210, 170, 2, true); /* ** done! */ exit(0); } 10: sample code 2-48 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 10.2 sample code without using the s1d13705 hal api this second sample demonstrates exactly the same sequence as the trst howerver the hal is not used, all manipulation is done by directly accessing the registers. /* **=========================================================================== ** sample2.c - sample code demonstating a direct access of the s1d13705. **------------------------------------------------------------------------- ** created 1998, vancouver design centre ** copyright (c) 1998, 1999 epson research and development, inc. ** all rights reserved. **------------------------------------------------------------------------- ** ** the sample code using direct s1d13705 access ** will configure for the following: ** ** 320x240 single color 4-bit stn ** 8 bpp color depth - 70 hz frame rate (6 mhz clki) ** ** notes: ** 1) this code is written to be compiled for use under 32-bit ** windows. in order to function the vxd file s1d13xxx.vxd must ** be in the \windows\system directory. ** 2) register setup is done with discreet writes rather than being table ** driven. this allows for clear commenting. it is more efficient to ** loop through the array writing each element to a control register. ** 3) the array of register values as produced by 1375cfg.exe is included ** here. i write the registers directly rather than refer to the register ** array in the sample code. ** **=========================================================================== */ #include 10: sample code s1d13705f00a programming notes epson 2-49 and examples (x27a-g-002-01) ** using a loop. */ unsigned char reg[0x20] = { 0x00, 0x23, 0xc0, 0x03, 0x27, 0xef, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; #define mem_size 0x14000/* 80 kb display buffer. */ typedef unsigned short word; /* some useful types */ typedef unsigned long dword; typedef unsigned char byte; typedef byte * pbyte; #define lobyte(w) ((byte)(w)) #define hibyte(w) ((byte)(((word)(w) >> 8) & 0xff)) #define set_reg(idx, val) (*(pregs + idx)) = (val) /*-----------------------------------------------------------------------*/ void main(void) { pbyte p13705; pbyte pregs; pbyte pmem; pbyte plut; int x, y, tmp; int bitsperpixel = 8; int width = 320; int height = 240; int offsetbytes; int rc; /* ** get a linear address we can use in our code to access the s1d13705. ** this is only needed to access the s1d13705 on the isa eval board. */ dword dwlinearaddress; rc = intelgetlinaddressw32(0xf00000, &dwlinearaddress); if (rc != 0) { printf("error getting linear address"); return; } p13705 = (pbyte)dwlinearaddress; pregs = p13705 + 0x1ffe0; /* ** check the revision code. exit if we don't find an s1d13705. */ if (0x24 != *pregs) { printf("didn't find an s1d13705"); return; } /* ** initialize the chip - after intialization the display will be ** setup for landscape use. ** normally a loop would be used to write the register array near ** the top of this file to the registers. ** for purposes of documenting the sample code, each register write ** is performed individually. */ /* ** register 01h: mode register 0 - color, 8-bit format 2 */ set_reg(0x01, 0x20); /* 10: sample code 2-50 epson s1d13705f00a programming notes and examples (x27a-g-002-01) ** register 02h: mode register 1 - 8bpp */ set_reg(0x02, 0xc0); /* ** register 03h: mode register 2 - normal power mode */ set_reg(0x03, 0x03); /* ** register 04h: horizontal panel size - 320 pixels - (320/8)-1 = 39 = 27h */ set_reg(0x04, 0x27); /* ** register 05h: vertical panel size lsb - 240 pixels ** register 06h: vertical panel size msb - (240 - 1) = 239 = efh */ set_reg(0x05, 0xef); set_reg(0x06, 0x00); /* ** register 07h - fpline start position - not used by stn */ set_reg(0x07, 0x00); /* ** register 08h - horizontal non-display period = (reg[08] + 4) * 8 ** = (0+4) * 8 = 32 pels ** - hndp and vndp are calculated to achieve the ** desired frame rate according to: ** ** pclk ** frame rate = --------------------------- ** (hdp + hndp) * (vdp + vndp) */ set_reg(0x08, 0x00); /* ** register 09h - fpframe start position - not used by stn */ set_reg(0x09, 0x00); /* ** register 0ah - vertical non-display register = 3 lines ** - calculated in conjunction with register 08h (hndp) to ** achieve the desired frame rate. */ set_reg(0x0a, 0x03); /* ** register 0bh - mod rate - not used by this panel */ set_reg(0x0b, 0x00); /* ** register 0ch - screen 1 start word address lsb ** register 0dh - screen 1 start word address msb ** - start address should be set to 0 */ set_reg(0x0c, 0x00); set_reg(0x0d, 0x00); /* ** register 0eh - screen 2 start word address lsb ** register 0fh - screen 2 start word address msb ** - set this start address to 0 too */ set_reg(0x0e, 0x00); set_reg(0x0f, 0x00); set_reg(0x10, 0x00); /* screen1/screen2 start address high bits. */ /* ** register 11h - memory address offset ** - used for setting memory to a width greater than the 10: sample code s1d13705f00a programming notes epson 2-51 and examples (x27a-g-002-01) ** display size. usually set to 0 during initialization ** and programmed to desired value later. */ set_reg(0x11, 0x00); /* ** register 12h - screen 1 vertical size lsb ** register 13h - screen 1 vertical size msb ** - set to maximum (i.e. 0x3ff). this register is used ** for split screen operation. normally it is set to ** maximum value. */ set_reg(0x12, 0xff); set_reg(0x13, 0x03); /* ** look-up table registers ** the lut is programmed at the end of the initialization sequence. */ /* ** register 18h - gpio configuration - set to 0 ** - '0' configures the gpio pins for input (power on default) */ set_reg(0x18, 0x00); /* ** register 19h - gpio status - set to 0 ** - this step has no real purpose. it sets the gpio ** pins low should gpio be set as outputs. */ set_reg(0x19, 0x00); /* ** register 1ah - scratch pad - set to 0 ** - use this register to store whatere state data your ** system may require. */ set_reg(0x1a, 0x00); /* ** register 1bh - portrait mode - set to 0 - disable portrait mode */ set_reg(0x1b, 0x00); /* ** register 1ch - line byte count - set to 0 - used only by portrait mode. */ set_reg(0x0c, 0x00); /* ** look-up table ** in this example we only set the first sixteen lut entries. ** in typical use all 256 entries would be setup. */ /* ** register 15h - look-up table address ** - set to 0 to start rgb sequencing at the first lut entry. */ set_reg(0x15, 0x00); /* ** register 17h - look-up table data ** - write 16 rgb triplets to the lut. */ plut = lut; for (tmp = 0; tmp < 16; tmp++) { set_reg(0x17, *plut);// set red plut++; set_reg(0x17, *plut);// set green plut++; set_reg(0x17, *plut);// set blue 10: sample code 2-52 epson s1d13705f00a programming notes and examples (x27a-g-002-01) plut++; } /* ** clear all of video memory by writing 81920 bytes of 0. */ pmem = p13705; for (tmp = 0; tmp < mem_size; tmp++) { *pmem = 0; pmem++; }; /* ** draw a 100x100 red rectangle in the upper left corner (0,0) ** of the display. */ for (y = 0; y < 100; y++) { /* ** set the memory pointer at the start of each line. ** pointer = mem_offset + (y * line_width * bpp / 8) + (x * bpp / 8) */ pmem = p13705 + (y * 320 * bitsperpixel / 8) + 0; for (x = 0; x < 100; x++) { *pmem = 0x4;/* draw a pixel with lut color 4 */ pmem++; } } /* ** wait for the user to press a key before continuing. */ printf("press any key to continue"); getch(); /* ** set and use portrait mode. */ /* ** clear the display, and all of video memory, by writing 81920 bytes ** of 0. this is done because an image in display memory is not rotated ** when the switch to portrait display mode occurs. */ pmem = p13705; for (tmp = 0; tmp < mem_size; tmp++) { *pmem = 0; pmem++; }; /* ** we will use the default portrait mode scheme so we have to adjust ** the rotated width to be a power of 2. ** (note: current height will become the rotated width) */ tmp = 1; while (height > (1 << tmp)) tmp++; height = (1 << tmp); offsetbytes = height * bitsperpixel / 8; /* ** set: ** 1) line byte count to size of the rotated width (i.e. current height) ** 2) start address to the offset of the width of the rotated display. ** (in portrait mode the start address registers point to bytes) */ set_reg(0x1c, (byte)offsetbytes); 10: sample code s1d13705f00a programming notes epson 2-53 and examples (x27a-g-002-01) offsetbytes--; set_reg(0x0c, lobyte(offsetbytes)); set_reg(0x0d, hibyte(offsetbytes)); /* ** set portrait mode. ** use the non-x2 (default) scheme so we don't have to re-calc the frame ** rate. mclk will be <= 25 mhz so we can leave auto-switch enabled. */ set_reg(0x1b, 0x80); /* ** draw a solid blue 100x100 rectangle centered on the display. ** starting co-ordinates, assuming a 320x240 display are: ** (320-100)/2 , (240-100)/2 = 110,70. */ for (y = 70; y < 180; y++) { /* ** set the memory pointer at the start of each line. ** pointer = mem_offset + (y * line_width * bpp / 8) + (x * bpp / 8) ** notice: as this is default portrait mode, the width is a power ** of two. in this case, we use a value of 256 pixels for ** our calculations instead of the panel dimension of 240. return -1; arr[0] = physaddr; arr[1] = 4 * 1024 * 1024; rc = deviceiocontrol(hdriver, ioctl_sed_map_physical_memory, &arr[0], 2 * sizeof(ulong), &retval, sizeof(ulong), &cbreturned, null); if (rc) *linaddr = retval; /* ** close the handle. ** this will dynamically unload the virtual device for win95. */ closehandle(hdriver); if (rc) return 0; return -1; } 10: sample code 2-54 epson s1d13705f00a programming notes and examples (x27a-g-002-01) 10.3 header files the header tles included here are the required for the hal sample to compile correctly. /* **=========================================================================== ** hal.h - header file for use with programs written to use the s1d13705 hal. **--------------------------------------------------------------------------- ** created 1998, vancouver design centre ** copyright (c) 1998, 1999 epson research and development, inc. ** all rights reserved. **=========================================================================== */ #ifndef _hal_h_ #define _hal_h_ #include "hal_regs.h" /*-------------------------------------------------------------------------*/ typedef unsigned char byte; typedef unsigned short word; typedef unsigned long dword; typedef unsigned int uint; typedef int bool; #ifdef intel typedef byte far *lpbyte; typedef word far *lpword; typedef uint far *lpuint; typedef dword far *lpdword; #else typedef byte *lpbyte; typedef word *lpword; typedef uint *lpuint; typedef dword *lpdword; #endif #ifndef lobyte #define lobyte(w) ((byte)(w)) #endif #ifndef hibyte #define hibyte(w) ((byte)(((uint)(w) >> 8) & 0xff)) #endif #ifndef loword #define loword(l) ((word)(dword)(l)) #endif #ifndef hiword #define hiword(l) ((word)((((dword)(l)) >> 16) & 0xffff)) #endif #ifndef makeword #define makeword(lo, hi) ((word)(((word)(lo)) | (((word)(hi)) << 8)) ) #endif #ifndef makelong #define makelong(lo, hi) ((long)(((word)(lo)) | (((dword)((word)(hi))) << 16))) #endif #ifndef true #define true 1 #endif #ifndef false #define false 0 #endif #define off 0 #define on 1 #define screen1 1 #define screen22 /* ** constants for hw rotate support */ #define default 0 10: sample code s1d13705f00a programming notes epson 2-55 and examples (x27a-g-002-01) #define landscape 1 #define portrait2 #ifndef null #ifdef __cplusplus #define null 0 #else #define null ((void *)0) #endif #endif /*-------------------------------------------------------------------------*/ /* ** size_version is the size of the version string (eg. "1.00") ** size_status is the size of the status string (eg. "b" for beta) ** size_revision is the size of the status revision string (eg. "00") */ #define size_version 5 #define size_status 2 #define size_revision 3 #ifdef enable_dpf /* debug_printf() */ #define dpf(exp) printf(#exp "\n") #define dpf1(exp) printf(#exp " = %d\n", exp) #define dpf2(exp1, exp2) printf(#exp1 "=%d " #exp2 "=%d\n", exp1, exp2) #define dpfl(exp) printf(#exp " = %x\n", exp) #else #define dpf(exp) ((void)0) #define dpf1(exp) ((void)0) #define dpfl(exp) ((void)0) #endif /*-------------------------------------------------------------------------*/ enum { err_ok = 0, /* no error, call was successful. */ err_failed, /* general purpose failure. */ err_unknown_device, /* */ err_invalid_parameter, /* function was called with invalid parameter. */ err_hal_bad_arg, err_toomany_devs }; /******************************************* * definitions for segetid() *******************************************/ #define product_id 0x24 enum { id_unknown, id_s1d13705_rev1 }; #define max_mem_addr81920 - 1 #define eighty_k81920 #define max_device 10 #define se_rsvd0 /******************************************* * definitions for internal calculations. *******************************************/ #define min_non_disp_x 32 #define max_non_disp_x 256 #define min_non_disp_y 2 #define max_non_disp_y 64 enum { red, green, blue }; 10: sample code 2-56 epson s1d13705f00a programming notes and examples (x27a-g-002-01) /*************************************************************************/ typedef struct taghalstruct { char szidstring[16]; word wdetectendian; word wsize; byte reg[max_reg + 1]; dword dwclki;/* input clock frequency (in khz) */ dword dwdispmem;/* */ word wframerate;/* */ } hal_struct; typedef hal_struct * phal_struct; #ifdef intel_16bit typedef hal_struct far * lphal_struct; #else typedef hal_struct * lphal_struct; #endif /*=========================================================================*/ /* function proto-types */ /*=========================================================================*/ /*---------------------------- initialization -----------------------------*/ int seregisterdevice( const lphal_struct lphalinfo ); int sesetinit( void ); int seinithal( void ); /*----------------------------- miscellaneous -----------------------------*/ int segetid( int *pid ); void segethalversion( const char **pversion, const char **pstatus, const char **pstatusrevision ); int sesetbitsperpixel( int nbitsperpixel ); int segetbitsperpixel( int *pbitsperpixel ); int segetbytesperscanline( int *pbytes ); int segetscreensize( int *width, int *height ); void sedelay( int nmilliseconds ); int segetlastusablebyte( long *lastbyte ); int sesethighperformance( bool onoff ); /*------------------------------- advanced --------------------------------*/ int sesethwrotate( int nmode ); int sesplitinit( word scrn1addr, word scrn2addr ); int sesplitscreen( int whichscreen, int visiblescanlines ); int sevirtinit( int xvirt, long *yvirt ); int sevirtmove( int nwhichscreen, int x, int y ); /*------------------------ register/memory access -------------------------*/ int segetreg( int index, byte *pvalue ); int sesetreg( int index, byte value ); int sereaddisplaybyte( dword offset, byte *pbyte ); int sereaddisplayword( dword offset, word *pword ); int sereaddisplaydword( dword offset, dword *pdword ); int sewritedisplaybytes( dword addr, byte val, dword count ); int sewritedisplaywords( dword addr, word val, dword count ); int sewritedisplaydwords( dword addr, dword val, dword count ); /*---------------------------------- power save ---------------------------*/ int sehwsuspend( int ndevid, bool val ); int sesetpowersavemode( int ndevid, int powersavemode ); /*----------------------------------- drawing -----------------------------*/ int sedrawline( int x1, int y1, int x2, int y2, dword color ); int sedrawrect( int x1, int y1, int x2, int y2, dword color, bool solidfill ); /*------------------------------ color ------------------------------------*/ int sesetlut( byte *plut ); int segetlut( byte *plut ); int sesetlutentry( int index, byte *pentry ); int segetlutentry( int index, byte *pentry ); #endif /* _hal_h_ */ /* **=========================================================================== 10: sample code s1d13705f00a programming notes epson 2-57 and examples (x27a-g-002-01) ** appcfg.h - application configuration information. **--------------------------------------------------------------------------- ** created 1998 - vancouver design centre ** copyright (c) 1998, 1999 epson research and development, inc. ** all rights reserved. **--------------------------------------------------------------------------- ** ** the data in this file was generated using 1375cfg.exe. ** ** the configureation parameters chosen were: ** 320x240 single color 4-bit stn ** 4 bpp - 100 hz frame rate (12 mhz clki) ** high performance enabled ** **=========================================================================== */ /************************************************************/ /* 13705 hal hdr (do not remove) */ /* hal_struct information generated by 1375cfg.exe */ /* copyright (c) 1998 epson research and development, inc. */ /* all rights reserved. */ /* */ /* include this file once in your primary source file */ /************************************************************/ hal_struct halinfo = { "13705 hal exe", /* id string */ 0x1234, /* detect endian */ sizeof(hal_struct), /* size */ 0x00, 0x20, 0xc0, 0x03, 0x27, 0xef, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6000, /* clki (khz) */ 0xf00000, /* display address */ 70, /* panel frame rate (hz) */ }; /* **=========================================================================== ** hal_regs.h **--------------------------------------------------------------------------- ** created 1998, epson research & development ** vancouver design center. ** copyright(c) seiko epson corp. 1998. all rights reserved. **=========================================================================== */ #ifndef __hal_regs_h__ #define __hal_regs_h__ /* ** 13705 register names */ #define reg_revision_code 0x00 #define reg_mode_register_0 0x01 #define reg_mode_register_1 0x02 #define reg_mode_register_2 0x03 #define reg_horz_panel_size 0x04 #define reg_vert_panel_size_lsb 0x05 #define reg_vert_panel_size_msb 0x06 #define reg_fpline_start_pos 0x07 #define reg_horz_nondisp_period 0x08 #define reg_fpframe_start_pos 0x09 #define reg_vert_nondisp_period 0x0a #define reg_mod_rate 0x0b #define reg_scrn1_start_addr_lsb 0x0c 10: sample code 2-58 epson s1d13705f00a programming notes and examples (x27a-g-002-01) #define reg_scrn1_start_addr_msb 0x0d #define reg_scrn2_start_addr_lsb 0x0e #define reg_scrn2_start_addr_msb 0x0f #define reg_scrn_start_addr_overflow 0x10 #define reg_memory_addr_offset 0x11 #define reg_scrn1_vert_size_lsb 0x12 #define reg_scrn1_vert_size_msb 0x13 #define reg_lut_addr 0x15 #define reg_lut_bank_select 0x16 #define reg_lut_data 0x17 #define reg_gpio_config 0x18 #define reg_gpio_status 0x19 #define reg_scratchpad 0x1a #define reg_portrait_mode 0x1b #define reg_line_byte_count 0x1c #define reg_not_present_1 0x1d /* ** warning!!! max_reg must be the last available register!!! */ #define max_reg 0x1d #endif /* __hal_regs_h__ */ /*-- -------------------------------------------------------------------------- ** ** copyright (c) 1998, 1999 epson research and development, inc. ** all rights reserved. ** ** module name: ** ** ioctl.h ** ** ** abstract: ** ** include file for s1d13xxx pci board driver. ** define the ioctl codes we will use. the ioctl code contains a command ** identifier, plus other information about the device, the type of access ** with which the file must have been opened, and the type of buffering. ** **---------------------------------------------------------------------------- */ #define sed_type file_device_controller // the ioctl function codes from 0x800 to 0xfff are for customer use. #define ioctl_sed_query_number_of_pci_boards \ ctl_code( sed_type, 0x900, method_buffered, file_any_access) #define ioctl_sed_map_pci_board \ ctl_code( sed_type, 0x901, method_buffered, file_any_access) #define ioctl_sed_map_physical_memory \ ctl_code( sed_type, 0x902, method_buffered, file_any_access) #define ioctl_sed_unmap_linear_memory \ ctl_code( sed_type, 0x903, method_buffered, file_any_access) s1d13705f00a embedded memory lcd controller utilities contents s1d13705f00a utilities epson 3-i contents 1 1375cfg c onfiguration p rogram ......................................................................................3-1 1.1 introduction................................................................................................................ ....................3-1 1.2 program requirements ........................................................................................................ .........3-1 installation ................................................................................................................... ...............3-1 usage.......................................................................................................................... ...............3-1 1.3 cfg tab..................................................................................................................... ...................3-2 panel information .............................................................................................................. .........3-3 miscellaneous options .......................................................................................................... .....3-5 system ......................................................................................................................... ..............3-6 lut control.................................................................................................................... ............3-7 message bar .................................................................................................................... ..........3-8 1.4 regs tab .................................................................................................................... .................3-9 1.5 buttons ..................................................................................................................... ...................3-10 open ........................................................................................................................... .............3-10 save ........................................................................................................................... ..............3-11 help........................................................................................................................... ...............3-11 exit ........................................................................................................................... ................3-11 1.6 comments .................................................................................................................... ...............3-12 2 1375show d emonstration p rogram ................................................................................3-13 2.1 1375show .................................................................................................................... .............3-13 s1d13705 supported evaluation platforms ............................................................................3-13 installation ................................................................................................................... .............3-13 usage.......................................................................................................................... .............3-14 comments....................................................................................................................... .........3-14 program messages ............................................................................................................... ...3-15 3 1375splt d isplay u tility ..................................................................................................3-16 3.1 1375splt .................................................................................................................... ...............3-16 s1d13705 supported evaluation platforms ............................................................................3-16 installation ................................................................................................................... .............3-16 usage.......................................................................................................................... .............3-17 1375splt example ............................................................................................................... ..3-17 program messages ............................................................................................................... ...3-18 4 1375virt d isplay u tility ...................................................................................................3-19 4.1 1375virt .................................................................................................................... ................3-19 s1d13705 supported evaluation platforms ............................................................................3-19 installation ................................................................................................................... .............3-19 usage.......................................................................................................................... .............3-20 1375virt example ............................................................................................................... ...3-20 program messages .............................................................................................................. ...3-21 5 1375play d iagnostic u tility ............................................................................................3-22 5.1 1375play .................................................................................................................... ...............3-22 s1d13705 supported evaluation platforms ............................................................................3-22 installation ................................................................................................................... .............3-22 usage.......................................................................................................................... .............3-23 1375play example ............................................................................................................... ..3-24 scripting ...................................................................................................................... .............3-24 comments....................................................................................................................... .........3-24 program messages ............................................................................................................... ...3-25 6 1375bmp d emonstraion p rogram ....................................................................................3-26 6.1 1375bmp..................................................................................................................... ................3-26 installation ................................................................................................................... .............3-26 contents 3-ii epson s1d13705f00a utilities usage .......................................................................................................................... ............ 3-26 comments ....................................................................................................................... ........ 3-26 program messages............................................................................................................... ... 3-27 7 1375pwr p ower s ave u tility ...........................................................................................3-28 7.1 1375pwr..................................................................................................................... ............... 3-28 s1d13705 supported evaluation platforms ............................................................................ 3-28 installation................................................................................................................... ............. 3-28 usage .......................................................................................................................... ............ 3-29 program messages............................................................................................................... ... 3-29 contents s1d13705f00a utilities epson 3-iii list of figures figure 1-1 1375cfg window ....................................................................................................... .........3-2 figure 1-2 panel information .................................................................................................... .............3-3 figure 1-3 miscellaneous options ................................................................................................ .........3-5 figure 1-4 system options ....................................................................................................... .............3-6 figure 1-5 error: frame rate .................................................................................................... .......3-6 figure 1-6 error: zero frame rate ............................................................................................... ....3-6 figure 1-7 look-up table control ................................................................................................ .........3-7 figure 1-8 regs window .......................................................................................................... ...........3-9 figure 1-9 1375cfg file open dialog ............................................................................................. ...3-10 figure 1-10 error: unable to read hal........................................................................................... ..3-10 figure 1-11 1375cfg save as dialog .............................................................................................. ....3-11 figure 1-12 error: unable to read hal........................................................................................... ..3-11 list of table table 1-1 mclk to pclk ratios................................................................................................... .......3-5 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-1 1 1375cfg c onfiguration p rogram 1.1 introduction 1375cfg is 32-bit windows program designed to calculate register values for the s1d13705. the user enters data such as the input clock frequency, panel width and height, and other panel speci? information. after calculating the register values the information can be used to con?ure executable ?es based on the s1d13705 hardware abstraction layer (hal) or written to ascii text ?es. 1375cfg can: read programs, based on the s1d13705 hal, modify the settings and write the changes back to the ?e. the ability to read, modify and write executable ?es bypasses having to recompile after con?uration changes. write c header ?es containing register settings which then can be used to initialize the s1d13705 registers in programs which do not use the hal. write ascii text ?es containing a list of the registers and the register values and the input clock and frame rate the register calculations are based on. 1.2 program requirements this program is designed to run under windows 95/98 or windows nt. installation there is no installation program for 1375cfg. installation to a local drive is done by copying 1375cfg.exe and 1375cfg.hlp to your hard drive and optionally creating a link on the windows desktop for easy access to the program. usage open the drive and folder where you copied 1375cfg.exe and double click the icon to start the program. optionally, if you created a link to the program on your desktop, double click the link icon. after starting you will be presented with a tabbed dialog box containing four buttons and two tabs: cfg and regs. the following sections will describe the using the tabs followed by a description of the buttons. x27a-b-001-01 1: 1375cfg configuration program 3-2 epson s1d13705f00a utilities (x27a-b-001-01) 1.3 cfg tab upon opening 1375cfg the user is present with a window which appears as in figure 1-1. the cfg tab is the dominant portion of the window and consists of four main sections: panel information (includes dimensions), look-up table, miscellaneous options, and system settings. each of these sections will be discussed in detail. figure 1-1 1375cfg window 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-3 panel information figure 1-2 panel information the panel information portion of cfg tab describes the panel to be connected to the s1d13705. this section of the 1375cfg dialog describes the panel connected to the s1d13705. each of the settings are described brie? below. mono / color - selects whether the attached panel is monochrome or color. select mono for monochrome panels or color for color panels. this option is stn speci? and is disabled if tft is selected. single / dual - selects whether the panel is a single stn or dual stn. select single for a single panel or dual for a dual panel. this option is stn speci? and is disabled if tft is selected. stn / tft - determines the technology used to construct the panel. select stn for passive panels or tft for active panels. selecting stn enables all the stn options and disables (grays out) the tft speci? settings. selecting tft enables the tft settings and disables stn speci? settings. 4 bit / 8 bit - these setting select the data width the panel requires. these radio buttons are stn/tft speci?. when stn is selected the options are ? bit?and ? bit? selecting a tft type panel changes these options to ? bit?and ?2 bit? select the data width as appropriate for your panel. note: panel data width is not the same as color depth. dimensions - the two boxes in the upper right corner of the cfg tab allow selecting the panel dimensions. in the left selection box enter the panel width in pixels and in the right selection box enter the panel height in pixels. values in the selection boxes can be either chosen from the drop-down list or typed directly into the edit portion of the selection box. mask fpshift - when selected causes the signal fpshift to be masked. this option is required by most newer monochrome panels. whenever either color panel or tft is selected this option is disabled. 1: 1375cfg configuration program 3-4 epson s1d13705f00a utilities (x27a-b-001-01) format 2 - determines the data clocking format for ? bit?single color panels. 8-bit single color panels typically use one of two data clocking formats arbitrarily named ?ormat 1?and ?ormat 2? selecting ?ormat 2?instructs the s1d13705 to use the second color panel data format. most newer panels and, to date, all color panels smaller than 640x480 use ?ormat 2? setting this attribute incorrectly will result in a garbled display but will not damage the panel. the display may appear ?ut in half?or possibly horizontally skewed. this option is stn speci? and is disabled if tft is selected. it is also disabled if the panel type selected to be 4-bit data or monochrome. frame repeat - is a feature for el panel support. el panels require a frame of repeated data as the cue to switch polarization. without this change in polarization panel quality deteriorates. when frame repeat is selected an internal counter causes the periodic repeat of one frame of modulated panel data. at a frame rate of 72 hz the repeat period is roughly one hour. when not selected the modulated image is never consecutively repeated. this option is stn speci? and is disabled if tft is selected. mod count - speci?s the number of fpline pulses between toggles of the mod signal. this setting is for passive panels only and is generally only required for older monochrome panels. when set to ??(default) the mod output signal toggles every fpframe. fpline start - speci?s the delay, in 8 pixel resolution, from the end of a line of display data (fpdat) to the leading edge of fpline. this ?ld is a tft speci? setting and is disabled if an stn panel is chosen. fpframe start - speci?s the number of lines between the last line of display data (fpdat) and the leading edge of fpframe. this ?ld is a tft speci? setting and is disabled if an stn panel is chosen. fpline / fpframe polarity - these settings control the sync pulse direction of the fpline and fpframe pulses in tft modes. select the appropriate pulse direction for the panel being connected. selecting 'lo' results in an active low sync pulse while 'hi' results in an active high pulse. these settings are tft speci? and are disabled when stn panel is selected. when an stn panel type is selected the pulse directions are preset to +ve, +ve. 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-5 miscellaneous options figure 1-3 miscellaneous options miscellaneous options cover several items which do not ? into other categories. hw video invert enable - when selected, enables the hardware video invert capability of the s1d13705. the s1d13705 supports inverted color output. the color inversion can be toggled by software or in response to a signal applied to pin fpdat11. in order for the hardware color inversion to succeed this option must be selected, or the software must enable this feature at run time. there are two methods of performing color inversion. in the ?st scheme the display memory data is inverted and the resulting color is derived from the corresponding look-up table element. (i.e. the inverse of color 0 would be whatever color was lut[ff] was set to. if element 0 and ff were both set to set to white then we would observe the inverse of white as being white). the second scheme is to invert the data as it comes out of the look-up table resulting in a true color inversion. the s1d13705 uses the second method. tft panels require all the fpdat control lines, as a result hardware color inversion is not possible when using tft panels. software invoked color inversion can be invoked when using tft panels. hw power save enable - select this option to enable hardware invoked power save modes. the s1d13705 supports two means of invoking a power save mode. in response to a software effected change or in response to input on the gpio0 pin. in order for the hardware power save mode to function this option must be selected. high performance - improves chip throughput at the expense of power consumption. when not selected the memory clock (mclk) signal is a divided down version of the pixel clock (pclk) signal. table 1 depicts the ratios when high performance is not selected. with slower mclk selections comes lower performance and also lower power use. this setting allows the user to trade off power consumption for system performance. selecting this option result in mclk equalling pclk at all display resolution. overall performance is increased but so is power consumption. swivelview mode - selecting this option causes register settings and timings to be saved for swivelview mode operation. table 1-1 mclk to pclk ratios color depth (bpp) ratio 1 mclk = pclk / 8 2 mclk = pclk / 4 4 mclk = pclk / 2 8 mclk = pclk 1: 1375cfg configuration program 3-6 epson s1d13705f00a utilities (x27a-b-001-01) alternate swivelview mode - selects the alternate mode. the s1d13705 supports two swivelview mode schemes. default swivelview mode offers slightly slower performance with the gain of lower power consumption. alternate swivelview mode is more ?xible and slightly faster at the expense of drawing more power. this option is only enable if swivelview mode is selected. note: the swivelview mode settings are intended primarily for the case where a developer de- sires a c header file set of register values for his own program. the hal is capable of performing rotations ?n the ?? most programs written for the hal will ignore this setting and set swivelview or landscape display modes as instructed by the user. system the options in the system section describe the items which are required for frame rate calculations and the location in cpu address space where the s1d13705 will be located. figure 1-4 system options memory location - this describes where in cpu address space the s1d13705 will be located. this setting is required by the hal to locate the s1d13705. frame rate - indicates the desired frame rate. 1375cfg will attempt to write register settings which result in the requested frame rate. if the frame rate cannot be reached then the following dialog inform the user of the problem. figure 1-5 error: frame rate a frame rate must be entered in order for 1375cfg to complete the frame rate calculations. if no frame rate is entered or the frame rate is set to 0 then the following dialog box will inform the user when they try to save the con?uration. figure 1-6 error: zero frame rate input clock - this ?ld speci?s the input clock being applied to the s1d13705 in khz. 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-7 lut control this section controls the color depth for the s1d13705 after initialization. figure 1-7 look-up table control select the desired color depth from the available options. color depth selections in this section are enabled or disabled dependent upon the selected panel dimensions. i.e. there is only enough memory to operate a 640x480 panel at 2 bit per pixel so the selections for 4 bpp and 8 bpp would be disabled when this panel size is selected. note: the primary use for the look-up table color depth settings are for a developer to derive a set of register values for inclusion in a program. most of the sample programs based on the hal override the color depth for testing purposes. 1: 1375cfg configuration program 3-8 epson s1d13705f00a utilities (x27a-b-001-01) message bar the message bar is used to convey con?uration information to the person using 1375cfg. these messages are intended to help the user in derive the best possible con?uration. currently there are three messages which may appear here: warning: hndp (???) is getting quite large. this message is declaring the horizontal non-display period is getting quite large 1375cfg uses a loop to determine the best values for both horizontal and vertical non-display periods. if the horizontal non-display period grows excessively large (greater than160 pixels) as result of the calculations this message is issued. larger hndp values usually result in fading of the display image.try increasing the frame rate or reducing the input clock to correct this problem. this warning may be ignored with the understanding that there may be a display image degradation. warning: vndp (???) is getting quite large. this message is declaring the vertical non-display period is getting quite large. the value (???) is the vndp that 13705 has calculated. 1375cfg uses a loop to determine the best values for both horizontal and vertical non-display periods. if the vertical non-display period grows excessively large (greater than 30 lines) as result of the calculations this message is issued. larger vndp values may result in image tearing, jitter or other display anomalies. try increasing the frame rate or reducing the input clock to correct this problem. this warning may be ignored with the understanding that there may be a display image degradation. warning: unable to set the frame rate based on the current settings. based on the current setting for horizontal and vertical size, input clock and desired frame rate it is not possible to calculate a combination of horsetail and vertical non-display times to satisfy the requested frame rate. typical causes for this message are incorrect input clock or frame rate values. the values may be excessively high or excessively low. correct the suspect value before attempting to save the con?uration. if this warning is ignored it will lead to the message box shown in figure 1-5 on page 3-6 or figure 1-6 on page 3-6 being displayed when the ?ave?button is clicked. 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-9 1.4 regs tab the regs tab displays the register values derived after converting the information on the cfg page in to register values. the automatic calculations may not result in precisely the register values required for a speci? use. for instance the hndp or vndp values may have to be tweaked for a particular panel. from this page the user can set speci? register to speci? values. figure 1-8 regs window not all the s1d13705 registers are represented on this page. for example; it makes no sense to represent reg[00], the revision code, which is read only. nor are the look-up table registers, reg[15] and reg[17], as they must be specially handled by the application after the majority of the s1d13705 registers have been initialized. typical use of 1375cfg involves using the cfg page to quickly set register values. after performing the initial setup on the cfg page the user should switch to the regs page and perform any register adjusting that must be done. important : do not return to the cfg page after making register adjustments on this page. doing so will result in an automatic recalculation of some register values and the possible loss of adjusted settings. 1: 1375cfg configuration program 3-10 epson s1d13705f00a utilities (x27a-b-001-01) 1.5 buttons outside of the page area of 1375cfg there are four buttons for reading and writing ?es, obtaining help or for exiting the program. the following sections describe these buttons. open click the open button to read the settings saved in an executable program based on the s1d13705 hardware abstraction layer. clicking the open button brings up the standard windows ?e open dialog. figure 1-9 1375cfg file open dialog from here the user selects the ?e to be opened. 1375cfg is capable of opening executable ?es based on the s1d13705 hal. typically the ?e extension for these ?e are .exe for intel platform executables and .s9 for 68k and sh3 platform executables. opening a ?e reads that ?es hal con?uration information. use the data read as a starting point in con?uring this or other ?es or to check on the current con?uration. if 1375cfg is unable locate the hal information in the selected ?e the following dialog box is displayed. figure 1-10 error: unable to read hal 1: 1375cfg configuration program s1d13705f00a utilities (x27a-b-001-01) epson 3-11 save click the save button to save the current con?uration settings. when clicked the standard windows ?e ?ave as?dialog box is displayed. figure 1-11 1375cfg save as dialog from the save as dialog box ?st select the type of ?e to save to in the ?ave as type:?edit ?ld. 1375cfg currently saves in three ?e formats. .exe ?es - are binary images containing a hal structure for execution on intel platforms .s9 ?es - are ascii binary format ?es used by several embedded systems. the .s9 ?e is a varia- tion of s19 ?es. .h ?es - are ascii c header ?es which can be included in other programs. if an executable ?e (.exe or .s9) is selected as the type of ?e to save to the ?e being saved to must already exist and be an s1d13705 hal based program. 1375cfg is cannot save to a non-existent program. if 1375cfg is unable to locate the hal information in the ?e being saved to the following dialog box is displayed. figure 1-12 error: unable to read hal help clicking on the help button will start the help ?e for 1375cfg. exit clicking on the exit button exits 1375cfg immediately. the user is not prompted to save any changes they may have made. 1: 1375cfg configuration program 3-12 epson s1d13705f00a utilities (x27a-b-001-01) 1.6 comments it is assumed that the 1375cfg user is familiar with s1d13705 hardware and software. refer to the ?1d13705 hardware functional speci?ation drawing of?e number x27a-a-001-02, and the ?1d13705 programming notes and examples manual, drawing of?e number x27a-g-002-01 for information. 2: 1375show demonstration program s1d13705f00a utilities (x27a-b-002-01) epson 3-13 2 1375show d emonstration p rogram 2.1 1375show 1375show is a program designed to demonstrate rudimentary display capabilities of the s1d13705. the display abilities are shown by drawing a pattern image to the video display at all supported color depths (1, 2, 4 and 8 bits-per-pixel) the 1375show display utility must be con?ured and/or compiled to work with your hardware platform. the program 1375cfg.exe can be used to con?ure 1375show. consult the ?375cfg configuration program , document number x27a-b-001-01, for more information on con?uring s1d13705 utilities. this software is designed to work in both embedded and personal computer (pc) environments. for the embedded environment, it is assumed that the system has a means of downloading software from the pc to the target platform. typically, this is done by serial communications. the pc uses a terminal program to send control commands and information to the target processor. alternatively, the pc can program an eprom, which is then placed in the target platform. some target platforms can also communicate with the pc via a parallel port connection, or an ethernet connection. s1d13705 supported evaluation platforms 1375show has been tested with the following s1d13705 supported evaluation platforms: pc system with an x86 processor. both 16-bit and 32-bit code is supported. m68ec000idp (integrated development platform) board, revision 3.0, with a motorola m68ec000 processor. sh3-lcevb board, revision b, with an hitachi sh-3 hd6417780 processor. if the platform you are using is different from the above, please see the ?1d13705 programming notes and examples manual, document number x26a-g-002-01. installation pc intel platform for 16-bit program version: copy the ?e 1375show.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. copy the ?e 1375show.exe to a directory that is in the dos path on your hard drive. embedded platform download the program 1375show to the system. x27a-b-002-01 2: 1375show demonstration program 3-14 epson s1d13705f00a utilities (x27a-b-002-01) usage pc platform : at the prompt, type: 1375show [/a][b=n][/l][/p [/alt]][/vertical][/noinit][/?] embedded platform : execute 1375show and at the prompt, type the command line argument(s). where: /a automatically cycle through all video modes. b=? starts 1375show at a user specified bit-per-pixel (bpp) level, where ? can be: 1, 2, 4, or 8. /l set landscape mode. /p set portrait mode. /alt use alternate portrait mode /vertical displays vertical line pattern. /update continuously update display memory. /noinit bypass register initialization and use values which are currently in the registers. /? displays the help screen. comments the /alt command line switch can only be used with the /p (portrait) mode switch. this switch will have no effect in landscape display modes. the intel 32-bit version of 1375show is designed to work under either windows 9x or windows nt. to install the 32-bit windows device driver s1d13xxx.vxd see the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. the 16-bit version of the program runs under dos with no dos extenders. the lack of a dos extender means that the 16-bit program can only be used on a hardware platform where the s1d13705 is addressed below 1mb. 2: 1375show demonstration program s1d13705f00a utilities (x27a-b-002-01) epson 3-15 program messages error: did not find a 13705 device. the hal was unable to read the revision code register on the s1d13705. ensure that the s1d13705 hardware is installed and that the hardware platform has been con?ured correctly. also check that the display memory address has been con?ured correctly. error: unable to locate/load s1d13xxx.vxd 1375play was unable to load a required driver. the ?e s1d13xxx.vxd should be located in x:\windows\system or in x:\winnt\system. if the ?e is not there, install it as described in the s1d13xxx 32-bit windows device driver installation guide, document number x00a-e-003- xx. error: an ioctl error occurred this message indicates an error at the io control layer occurred. the usual cause for this is an incorrect hardware con?uration. error: the hal returned an unknown error this message should never be displayed, it indicates that 1375show is unable to determine the cause of an error returned from the hal. error: could not initialize device the call to initialize the s1d13705 registers failed. not enough memory for www x hhh x bpp!! this message is printed if there is insuf?ient display memory to show a complete image with a width of www pixels, a height of hhh pixels and a color depth of bpp bit-per-pixel. in this case the mode is skipped and the next display mode is attempted. 3: 1375splt display utility 3-16 epson s1d13705f00a utilities (x27a-b-003-01) 3 1375splt d isplay u tility 3.1 1375splt 1375splt demonstrates s1d13705 split screen capability by showing two different areas of display memory on the screen simultaneously. screen 1 memory is located at the start of the display buffer and is ?led with horizontal bars. screen 2 memory is located immediately after screen 1 in the display buffer and is ?led with vertical bars. on either user input or elapsed time, the line compare register value is changed to adjust the amount of display area taken up by each screen. the 1375splt display utility must be con?ured and/or compiled to work with your hardware platform. the program 1375cfg.exe can be used to con?ure 1375splt. consult the ?375cfg configuration program , document number x27a-b-001-01, for more information on con?uring s1d13705 utilities. this software is designed to work in both embedded and personal computer (pc) environments. for the embedded environment, it is assumed that the system has a means of downloading software from the pc to the target platform. typically, this is done by serial communications. the pc uses a terminal program to send control commands and information to the target processor. alternatively, the pc can program an eprom, which is then placed in the target platform. some target platforms can also communicate with the pc via a parallel port connection, or an ethernet connection. s1d13705 supported evaluation platforms 1375splt has been tested with the following s1d13705 supported evaluation platforms: pc system with an x86 processor. both 16-bit and 32-bit code is supported. m68ec000idp (integrated development platform) board, revision 3.0, with a motorola m68ec000 processor. sh3-lcevb board, revision b, with an hitachi sh-3 hd6417780 processor. if the platform you are using is different from the above, please see the ?1d13705 programming notes and examples manual , document number x26a-g-002-01. installation pc intel platform for 16-bit program version: copy the ?e 1375splt.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the s1d13xxx 32-bit windows device driver installation guide, document number x00a-e-003-xx. copy the ?e 1375splt.exe to a directory that is in the dos path on your hard drive. embedded platform download the program 1375splt to the system. x27a-b-003-01 3: 1375splt display utility s1d13705f00a utilities (x27a-b-003-01) epson 3-17 usage pc platform : at the prompt, type 1375splt [/a] [/?] embedded platform : execute 1375splt and at the prompt, type the command line argument. where : no argument enables manual split screen operation /a enables automatic split screen operation (a timer is used to move screen 2) /? display the help screen after starting 1375splt the following keyboard commands are available. manual mode: , u move screen 2 up , d move screen 2 down home covers screen 1 with screen 2 end displays only screen 1 automatic mode: any key change the direction of split screen movement (for pc only) both modes: b changes the color depth (bits-per-pixel) esc exits 1375splt 1375splt example 1. type ?375splt /a?to automatically move the split screen. 2. press ??to change the color depth from 1 bit-per-pixel to 2 bit-per-pixel. 3. repeat step 2 for the remaining color depths (4 and 8 bit-per-pixel). 4. press 3: 1375splt display utility 3-18 epson s1d13705f00a utilities (x27a-b-003-01) program messages error: did not find a 13705 device. the hal was unable to read the revision code register on the s1d13705. ensure that the s1d13705 hardware is installed and that the hardware platform has been con?ured correctly. also check that the display memory address has been con?ured correctly. error: unable to locate/load s1d13xxx.vxd 1375play was unable to load a required driver. the ?e s1d13xxx.vxd should be located in x:\windows\system or in x:\winnt\system. if the ?e is not there, install it as described in the s1d13xxx 32-bit windows device driver installation guide, document number x00a-e-003- xx. error: an ioctl error occurred this message indicates an error at the io control layer occurred. the usual cause for this is an incorrect hardware configuration. error: the hal returned an unknown error this message should never be displayed, it indicates that 13705solt is unable to determine the cause of an error returned from the hal. not enough memory for www x hhh x bpp!! this message is displayed if there is insuf?ient display memory to contain two complete images with a width of www pixels, a height of hhh pixels, and a color depth of bpp bit-per-pixel. in this case the mode is skipped and the next display mode is attempted. 4: 1375virt display utility s1d13705f00a utilities (x27a-b-004-01) epson 3-19 4 1375virt d isplay u tility 4.1 1375virt 1375virt demonstrates the virtual display capability of the s1d13705. a virtual display is where the image to be displayed is larger than the physical display device. the display surface is used a viewing window. the entire image can be seen only by panning and scrolling. the 1375virt display utility must be con?ured and/or compiled to work with your hardware platform. the program 1375cfg.exe can be used to con?ure 1375virt. consult the ?375cfg configuration program , document number x27a-b-001-01, for more information on con?uring s1d13705 utilities. this software is designed to work in both embedded and personal computer (pc) environments. for the embedded environment, it is assumed that the system has a means of downloading software from the pc to the target platform. typically, this is done by serial communications. the pc uses a terminal program to send control commands and information to the target processor. alternatively, the pc can program an eprom, which is then placed in the target platform. some target platforms can also communicate with the pc via a parallel port connection, or an ethernet connection. s1d13705 supported evaluation platforms 1375virt has been tested with the following s1d13705 supported evaluation platforms: pc system with an x86 processor. m68ec000idp (integrated development platform) board, revision 3.0, with a motorola m68ec000 processor. sh3-lcevb board, revision b, with an hitachi sh-3 hd6417780 processor. if the platform you are using is different from the above, please see the ?1d13705 programming notes and examples manual, document number x26a-g-002-01. installation pc intel platform for 16-bit program version: copy the ?e 1375virt.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. copy the ?e 1375virt.exe to a directory that is in the dos path on your hard drive. embedded platform download the program 1375virt to the system. x27a-b-004-01 4: 1375virt display utility 3-20 epson s1d13705f00a utilities (x27a-b-004-01) usage pc platform : at the prompt, type 1375virt [/a] [/l] [/p] [/alt] [/w=???] . embedded platform : execute 1375virt and at the prompt, type the command line argument. where: no argument panning and scrolling is performed manually (defaults to virtual width = = physical width x 2 and maximum virtual height) /a panning and scrolling is performed automatically /l force landscape display mode to be set /p force portrait display mode to be set /alt enable alternate portrait mode. selecting this option implies /p /w=??? speci?s the virtual display width which includes both on-screen and off-screen size t he maximum virtual width, not including display area, for each display mode is: 1 bpp ?4096 pixels 2 bpp ?2048 pixels 4 bpp ?1024 pixels 8 bpp ?512 pixels the following keyboard commands are for navigation within the program. manxual mode: scrolls up scrolls down pans to the left pans to the right home moves the display screen so that the upper right of the virtual screen shows in the upper right of the display end moves the display screen so that the lower left of the virtual screen shows in the lower left of the display automatic mode: any key changes the direction of screen both modes: b changes the color depth (bits-per-pixel) esc exits 1375virt 1375virt example 5. type ?375virt /a?to automatically pan and scroll. 6. press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. 7. repeat steps 1 and 2 for the remaining color depths (4 and 8 bit-per-pixel). 8. press 4: 1375virt display utility s1d13705f00a utilities (x27a-b-004-01) epson 3-21 program messages error: did not find a 13705 device. the hal was unable to read the revision code register on the s1d13705. ensure that the s1d13705 hardware is installed and that the hardware platform has been con?ured correctly. also check that the display memory address has been con?ured correctly. error: unable to locate/load s1d13xxx.vxd 1375play was unable to load a required driver. the file s1d13xxx.vxd should be located in x:\windows\system or in x:\winnt\system. if the file is not there, install it as described in the s1d13xxx 32-bit windows device driver installation guide, document number x00a-e-003- xx. error: an ioctl error occurred this message indicates an error at the io control layer occurred. the usual cause for this is an incorrect hardware con?uration. error: the hal returned an unknown error this message should never be displayed, it indicates that 1375virt is unable to determine the cause of an error returned from the hal. unable to use virtual mode at xx bpp this message is displayed if there is insuf?ient display memory to show a complete virtual image. speci?ally, the maximum number of lines for the image is calculated using the current virtual width. if the number of possible lines is less than the physical display size this message is displayed. try restarting the program and manually specify a smaller virtual width. 5: 1375play diagnostic utility 3-22 epson s1d13705f00a utilities (x27a-b-005-01) 5 1375play d iagnostic u tility 5.1 1375play 1375play is a utility which allows the user to easily read/write the s1d13705 registers, look-up table and display memory. the user interface for 1375play is similar to the dos debug program; commands are received from the standard input device, and output is sent to the standard output device (console for intel and terminal for embedded platforms). this utility requires the target platform to support standard io. 1375play commands can be entered interactively using a keyboard/monitor or they can be executed from a script ?e. scripting is a powerful feature which allows command sequences played back from a ?e thus avoiding having to retype lengthy sequences. the 1375play display utility must be con?ured and/or compiled to work with your hardware platform. the program 1375cfg.exe can be used to con?ure 1375play. consult the ?375cfg configuration program , document number x27a-b-001-01, for more information on con?uring s1d13705 utilities. this software is designed to work in both embedded and personal computer (pc) environments. for the embedded environment, it is assumed that the system has a means of downloading software from the pc to the target platform. typically, this is done by serial communications. the pc uses a terminal program to send control commands and information to the target processor. alternatively, the pc can program an eprom, which is then placed in the target platform. some target platforms can also communicate with the pc via a parallel port connection, or an ethernet connection. s1d13705 supported evaluation platforms 1375play has been tested with the following s1d13705 supported evaluation platforms: pc system with an x86 processor. both 16-bit and 32-bit code is supported. m68ec000idp (integrated development platform) board, revision 3.0, with a motorola m68ec000 processor. sh3-lcevb board, revision b, with an hitachi sh-3 hd6417780 processor. if the platform you are using is different from the above, please see the ?1d13705 programming notes and examples manual, document number x26a-g-002-01. installation pc intel platform for 16-bit program version: copy the ?e 1375play.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. copy the ?e 1375play.exe to a directory that is in the dos path on your hard drive. embedded platform download the program 1375play to the system. x27a-b-005-01 5: 1375play diagnostic utility s1d13705f00a utilities (x27a-b-005-01) epson 3-23 usage pc platform : at the prompt, type 1375play [/?] . embedded platform : execute 1375play and at the prompt, type the command line argument. where : /? displays program revision information. the following commands are valid within the 1375play program. x index [data] reads/writes the registers. writes data to the register specified by the index when ?ata?is specified; otherwise the register is read. xa reads all registers. l index [data1 data2 data3] reads/writes look-up table (lut) values. writes data to the lut index when ?ata?is specified; otherwise the lut index is read. data must consist of 3 bytes: 1 red, 1 green, 1 blue. and range in value from 0x00 to 0x0f. la reads all lut values. f[w] addr1 addr2 data . . . fills bytes or words from address 1 to address 2 with data. data can be multiple values (e.g. f 0 20 1 2 3 4 fills address 0 to 0x20 with a repeating pattern of 1 2 3 4 ). r[w] addr [count] reads ?ount?of bytes or words from the address specified by ?ddr? if ?ount?is not specified, then 16 bytes/words are read. w[w] addr data . . . writes bytes or words of data to address specified by ?ddr? data can be multiple values (e.g. w 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0 ). i initializes the chip with user specified configuration. m [bpp] returns information about the current mode. if ?pp?is specified then set the requested color depth. p 0|1|2 sets software power save mode 0-2. power save mode 0 is normal operation. h [lines] halts after specified lines of display. this feature halts the display during long read operations to prevent data from scrolling off the display. set 0 to disable. q quits this utility. ? displays help information. 5: 1375play diagnostic utility 3-24 epson s1d13705f00a utilities (x27a-b-005-01) 1375play example type ?375play?to start the program. type "?" for help. type "i" to initialize the registers. type "xa" to display the contents of the registers. type "x 5" to read register 5. type "x 3 10" to write 10 hex to register 3. type "f 0 ffff aa" to ?l the ?st ffff hex bytes of display memory with aa hex. type "f 0 1 fffff aa" to ?l 2m bytes of display memory. type "r 0 ff" to read the ?st 100 hex bytes of display memory. type "q" to exit the program. scripting 1375play can be driven by a script ?e. this is useful when: there is no standard display output to monitor command entry and results. various registers must be quickly changed faster than can achieved by typing. the same series of keystrokes is being entered time and again. a script ?e is an ascii text ?e with one 1375play command per line. all scripts must end with a ??(quit) command in order to return control to the operating system. the semi-colon is used as a comment delimitor. everything on a line after the semi-colon will be ignored. on a pc platform, a typical script command line is: ?375play < dumpregs.scr > results? this causes the script ?e ?umpregs.scr?to be interpreted and the results to be sent to the ?e ?esults. example 1 : the script ?e ?umpregs.scr can be created with and text editor and will look like the following: ; this ?e initializes the s1d13705 and reads the registers i; initialize the registers. xa; dump all the registers la; and the lut q; exit comments all numeric values are considered to be hexadecimal unless identi?d otherwise. for example, 10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal. redirecting commands from a script ?e (pc platform) allows those commands to be executed as though they were typed. 5: 1375play diagnostic utility s1d13705f00a utilities (x27a-b-005-01) epson 3-25 program messages >>> warning: did not detect s1d13705 <<< the hal was unable to read the revision code register on the s1d13705. ensure that the s1d13705 hardware is installed and that the hardware platform has been con?ured correctly. also check that the display memory address has been con?ured correctly. error: unable to locate/load s1d13xxx.vxd 1375play was unable to load a required driver. the ?e s1d13xxx.vxd should be located in x:\windows\system or in x:\winnt\system. if the ?e is not there, install it as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e- 003-xx. error: an ioctl error occurred this message indicates an error at the io control layer occurred. the usual cause for this is an incorrect hardware con?uration. error: the hal returned an unknown error this message should never be displayed, it indicates that 1375play is unable to determine the cause of an error returned from the hal. 6: 1375bmp demonstraion program 3-26 epson s1d13705f00a utilities (x27a-b-006-01) 6 1375bmp d emonstraion p rogram 6.1 1375bmp 1375bmp is a demonstration program for the s1d13705 which can read and display .bmp format (windows bitmap) ?es. the 1375bmp display utility is designed to operate on an x86 based personal computer. there are both 16-bit and 32-bit versions of 1375bmp. the 16-bit version is for use under dos when the s1d13705 evaluation board has been con?ured for d0000. the 32-bit version is intended for use under win32. before use 1375bmp must be con?ured for the display system. consult documentation for the program 1375cfg.exe which can be used to con?ure 1375bmp. 1375bmp is not supported on non-pc platforms. installation for 16-bit program version: copy the ?e 1375bmp.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. copy the ?e 1375bmp.exe to a directory that is in the dos path on your hard drive. usage at the prompt, type: 1375bmp bmp_file [/a[time]] [/l] [/p] [/noinit] [/?] . where: bmp_file the name of the file to display /a[time] automatic mode returns to the operating system after ?ime?seconds. if time is not specified the default is 5 seconds. this option is intended for use with batch files to automate displaying a series of images. /l override default configuration settings and set landscape display mode. /p override default configuration settings and set portrait display mode. /noinit bypass the register initialization and use the current setup use this option to override changes that take place to the timing registers /? displays the help screen comments 1375bmp currently views only windows bmp format images. x27a-b-006-01 6: 1375bmp demonstraion program s1d13705f00a utilities (x27a-b-006-01) epson 3-27 program messages error: did not find an s1d13705 device. the hal was unable to locate an s1d13705 at the con?ured address. check that the correct physical address was con?ured into 1375bmp.exe error: unable to locate/load s1d13xxx.vxd the ?e s1d13xxx.vxd is required by the 32-bit version of the 1375bmp. check that the .vxd ?e is in c:\windows\system. if the ?e is not there, install it as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. error: an ioctl error occurred. the device driver s1d13xxx.vxd was unable to assign memory. check that the pc hardware is con?ured correctly and that 1375bmp has been con?ured with the correct memory location. error: the hal returned an unknown error. this error message should never bee seen. contact erd. error: could not initialize device. the hal failed to initialize the s1d13705. failed to open .bmp file '?.....?' 1375bmp was unable to open the .bmp ?e ?.....? speci?d on the command line. ?.....? is not a valid bitmap file. while performing validity checks it was determined that the ?e ?.....? is either not a valid .bmp ?e or is of an unsupported format. error: unable to set a suitable display mode. 1375bmp was unable to set a display mode to view the image with. error: currently unable to process images greater than 8 bpp. 1375bmp can decode images of 8bpp or less color depth. try reducing the color depth of your image. error: image larger than display memory size. the amount of memory required by this image is more than the amount of memory available to the s1d13705. try choosing a smaller image. error: unable to allocate enough memory to decode the image. in order to decode a .bmp image 1375bmp needs to allocate some additional system memory. this message is seen if the call to allocate additional memory fails. 7: 1375pwr power save utility 3-28 epson s1d13705f00a utilities (x27a-b-007-01) 7 1375pwr p ower s ave u tility 7.1 1375pwr the 1375pwr power save utility is a tool to assist in the testing of the software and hardware power save modes. refer to the section titled ?ower save modes?in the ?1d13705 programming notes and examples manual, document number x26a-g-002-01, and the ?1d13705 functional hardware speci?ation , document number x26a-a-001-02 for further information. the 1375pwr utility must be con?ured and/or compiled to work with your hardware platform. consult documentation for the program 1375cfg.exe which can be used to con?ure 1375pwr. this software is designed to work in both embedded and personal computer (pc) environments. for the embedded environment, it is assumed that the system has a means of downloading software from the pc to the target platform. typically this is done by serial communications, where the pc uses a terminal program to send control commands and information to the target processor. alternatively, the pc can program an eprom, which is then placed in the target platform. some target platforms can also communicate with the pc via a parallel port connection, or an ethernet connection. s1d13705 supported evaluation platforms 1375pwr has been designed to work with the following s1d13705 supported evaluation platforms: pc system with an x86 processor. both 16-bit and 32-bit code is supported. m68ec000idp (integrated development platform) board, revision 3.0, with a motorola m68ec000 processor. sh3-lcevb board, revision b, with an hitachi sh-3 hd6417780 processor. if the platform you are using is different from the above, please see the s1d13705 ?rogramming notes and examples manual, document number x26a-g-002-01. installation pc platform for 16-bit program version: copy the ?e 1375pwr.exe to a directory that is in the dos path on your hard drive. for 32-bit program version: install the 32-bit windows device driver s1d13xxx.vxd as described in the ?1d13xxx 32-bit windows device driver installation guide , document number x00a-e-003-xx. copy the ?e 1375pwr.exe to a directory that is in the dos path on your hard drive. embedded platform download the program 1375pwr to the system. x27a-b-007-01 7: 1375pwr power save utility s1d13705f00a utilities (x27a-b-007-01) epson 3-29 usage pc platform : at the prompt, type 1375pwr [s0] [s1] [h0] [h1] . embedded platform: execute 1375pwr and at the prompt, type the command line argument. where :s0 resets software power save mode s1 sets software power save mode h0 resets (disables) hardware power save mode (reg[03h] bit 2) h1 sets (enables) hardware power save mode (reg[03h] bit 2) /? displays this usage message program messages error: did not find a 13705 device. the hal was unable to read the revision code register on the s1d13705. ensure that the s1d13705 hardware is installed and that the hardware platform has been con?ured correctly. also check that the display memory address has been con?ured correctly. error: unable to locate/load s1d13xxx.vxd 1375play was unable to load a required driver. the ?e s1d13xxx.vxd should be located in x:\windows\system or in x:\winnt\system. if the ?e is not there, install it as described in the s1d13xxx 32-bit windows device driver installation guide, document number x00a-e-003- xx. error: an ioctl error occurred this message indicates an error at the io control layer occurred. the usual cause for this is an incorrect hardware con?uration. error: the hal returned an unknown error this message should never be displayed, it indicates that 1375show is unable to determine the cause of an error returned from the hal. software power save mode set. this message is a con?mation that the register setting to enable software power save mode has been set. software power save mode reset. this message is a con?mation that the register setting to disable software power save mode has been set. hardware power save mode is now enabled. this message con?ms that hardware initiated power save mode has been enabled. the s1d13705 will enter a hardware power save mode upon application of the appropriate logic level to the hardware power save mode input pin. hardware power save mode is now disabled. this message con?ms that the register setting to disable hardware initiated power save mode has been set. in this state the s1d13705 should ignore the state of the hardware power save mode input pin. 7: 1375pwr power save utility 3-30 epson s1d13705f00a utilities (x27a-b-007-01) this page is blank. s1d13705f00a embedded memory lcd controller s5u13705b00c r ev .1.0 isa bus evaluation board user? manual contents s5u13705b00c rev. 1.0 isa bus evaluation epson 4-i board user? manual contents 1i ntroduction .........................................................................................................................4-1 1.1 features .................................................................................................................... ....................4-1 2i nstallation and c onfiguration ...........................................................................................4-2 3 lcd i nterface p in m apping .................................................................................................4-3 4 cpu/b us i nterface c onnector p inouts ..............................................................................4-4 5h ost b us i nterface p in m apping .........................................................................................4-6 6t echnical d escription ..........................................................................................................4-7 6.1 embedded memory support ..................................................................................................... ....4-7 6.2 isa bus support ............................................................................................................. ...............4-8 6.2 display adapter card support .........................................................................................4-8 6.2 expanded memory manager support ..............................................................................4-8 6.3 non-isa bus support ......................................................................................................... ...........4-8 6.4 decoding logic.............................................................................................................. ................4-9 6.5 clock input support ......................................................................................................... ..............4-9 6.6 lcd panel voltage setting................................................................................................... .........4-9 6.7 monochrome lcd panel support ................................................................................................ .4-9 6.8 color passive lcd panel support ............................................................................................. ...4-9 6.9 color tft/d-tfd lcd panel support.........................................................................................4- 10 6.10 power save modes ........................................................................................................... ..........4-10 6.11 adjustable lcd panel negative power supply ...........................................................................4-10 6.12 adjustable lcd panel positive power supply ............................................................................4-10 6.13 cpu/bus interface header strips............................................................................................ ....4-10 7p arts l ist ...........................................................................................................................4-11 8s chematic d iagrams ...........................................................................................................4-12 contents 4-ii epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual list of figures figure 8-1 s5u13705b00c schematic diagram (1 of 4) .................................................................... 4-12 figure 8-2 s5u13705b00c schematic diagram (2 of 4) .................................................................... 4-13 figure 8-3 s5u13705b00c schematic diagram (3 of 4) .................................................................... 4-14 figure 8-4 s5u13705b00c schematic diagram (4 of 4) .................................................................... 4-15 list of tables table 2-1 configuration dip switch settings ..................................................................................... .. 4-2 table 2-2 host bus selection.................................................................................................... ........... 4-2 table 2-3 jumper settings ....................................................................................................... ............ 4-2 table 3-1 lcd signal connector (j5) pinout ...................................................................................... . 4-3 table 4-1 cpu/bus connector (h1) pinout ........................................................................................ 4 -4 table 4-2 cpu/bus connector (h2) pinout ........................................................................................ 4 -5 table 5-1 host bus interface pin mapping ........................................................................................ .. 4-6 1: introduction s5u13705b00c rev. 1.0 isa bus evaluation epson 4-1 board user? manual (x27a-g-005-01) 1i ntroduction this manual describes the setup and operation of the s5u13705b00c rev. 1.0 evaluation board. implemented using the s1d13705 embedded memory color lcd controller, the s5u13705b00c board is designed for the 16-bit isa bus environment. to accommodate other bus architectures, the s5u13705b00c board also provides cpu/bus interface connectors. for more information regarding the s1d13705, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. 1.1 features 80-pin qfp14 package. smt technology for all appropriate devices. 4/8-bit monochrome and color passive lcd panel support. 9/12-bit lcd tft/d-tfd panel support. selectable 3.3v or 5v lcd panel support. oscillator support for clki (up to 50mhz with internal clock divider or 25mhz with no internal clock divider). embedded 80k byte sram display buffer for 1/2/4 bit-per-pixel (bpp), 2/4/16-level gray shade display and 1/2/4/8 bpp, 2/4/16/256 level color display. support for software and hardware power save modes. on-board adjustable lcd bias positive power supply (+23v to +40v). on-board adjustable lcd bias negative power supply (-23v to -14v). 16-bit isa bus support. cpu/bus interface header strips for non-isa bus support. 2: installation and configuration 4-2 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 2i nstallation and c onfiguration the s1d13705 has four con?uration inputs, cnf[3:0], which are read on the rising edge of reset# and are fully con?urable on this evaluation board. one six-position dip switch is provided on the board to con?ure the four con?uration inputs, select the s5u13705b00c memory/register start address, and enable/disable hardware power save mode. the following settings are recommended when using the s5u13705b00c with the isa bus. table 2-1 con?uration dip switch settings switch signal closed (0 or low) open (1 or high) s1-1 cnf0 see ?ost bus selection?table below see ?ost bus selection?table below s1-2 cnf1 s1-3 cnf2 s1-4 cnf3 little endian big endian s1-5 addr memory/register start address = c0000h memory/register start address = f00000h s1-6 gpio0 hardware suspend disable hardware suspend enable = recommended settings (con?ured for isa bus support) table 2-2 host bus selection s1-3 s1-2 s1-1 bs# host bus interface 0 0 0 x sh-4 bus interface 0 0 1 x sh-3 bus interface 0 1 0 x reserved 0 1 1 x mc68k bus interface #1, 16-bit 1 0 0 x reserved 1 0 1 x mc68k bus interface #2, 16-bit 1100 reserved 1101 reserved 1110 generic #1, 16-bit 1 1 1 1 generic #2, 16-bit = recommended settings (con?ured for isa bus support) table 2-3 jumper settings description 1-2 2-3 jp1 iov dd selection 5.0v iov dd 3.3v iov dd jp2 bs# signal selection pulled up to iov dd no connection jp3 rd/wr# signal selection pulled up to iov dd no connection jp4 lcd panel voltage selection 5v lcd panel 3.3v lcd panel jp5 lcdpwr polarity active low (?cdpwr#? active high (?cdpwr? = recommended settings (jp1 through jp3 con?ured for isa bus support) 3: lcd interface pin mapping s5u13705b00c rev. 1.0 isa bus evaluation epson 4-3 board user? manual (x27a-g-005-01) 3 lcd i nterface p in m apping note: 1.un-used gpio pins must be connected to io v dd . 2.inverse video is enabled on fpdat11 by reg[02h] bit 1. table 3-1 lcd signal connector (j5) pinout connector single passive panel dual passive panel color tft/d-tfd pin name pin # color mono color mono 4-bit 8-bit 8-bit alternate format 4-bit 8-bit 8-bit 8-bit 9-bit 12-bit bfpdat0 1 driven 0 d0 ld0 driven 0 d0 d0 ld0 r2 r3 bfpdat1 3 driven 0 d1 ld1 driven 0 d1 d1 ld1 r1 r2 bfpdat2 5 driven 0 d2 ld2 driven 0 d2 d2 ld2 r0 r1 bfpdat3 7 driven 0 d3 ld3 driven 0 d3 d3 ld3 g2 g3 bfpdat4 9 d0 d4 ud0 d0 d4 d4 ud0 g1 g2 bfpdat5 11 d1 d5 ud1 d1 d5 d5 ud1 g0 g1 bfpdat6 13 d2 d6 ud2 d2 d6 d6 ud2 b2 b3 bfpdat7 15 d3 d7 ud3 d3 d7 d7 ud3 b1 b2 bfpdat8 17 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 b0 b1 bfpdat9 19 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 r0 bfpdat10 21 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 g0 bfpdat11 23 gpio4/ inverse video gpio4/ inverse video gpio4/ inverse video gpio4/ inverse video gpio4/ inverse video gpio4/ inverse video gpio4/ inverse video gpio4 b0 bfpshift 33 fpshift fpshift fpshift fpshift fpshift fpshift fpshift fpshift fpshift bfpshift2 35 fpshift2 bfpline 37 fpline fpline fpline fpline fpline fpline fpline fpline fpline bfp- frame 39 fpfram e fpfram e fpfram e fpfram e fpfram e fpfram e fpfram e fpfram e fpfram e gnd 2-26 (even pins) gnd gnd gnd gnd gnd gnd gnd gnd gnd n / c 28 vlcd 30 lcd panel negative bias voltage (-24v to -14v) lcdv cc 32 +3.3v or +5v (selectable with jp4) +12v 34 +12v +12v +12v +12v +12v +12v +12v +12v +12v vddh 36 lcd panel positive bias voltage (+23v to +40v) bdrdy 38 mod mod mod mod mod mod drdy drdy blcdpwr 40 lcdpwr lcdpwr lcdpwr lcdpwr lcdpwr lcdpwr lcdpwr lcdpwr lcdpwr 4: cpu/bus interface connector pinouts 4-4 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 4 cpu/b us i nterface c onnector p inouts table 4-1 cpu/bus connector (h1) pinout connector pin no. cpu/bus pin name comments 1 sd0 connected to db0 of the s1d13705 2 sd1 connected to db1 of the s1d13705 3 sd2 connected to db2 of the s1d13705 4 sd3 connected to db3 of the s1d13705 5 gnd ground 6 gnd ground 7 sd4 connected to db4 of the s1d13705 8 sd5 connected to db5 of the s1d13705 9 sd6 connected to db6 of the s1d13705 10 sd7 connected to db7 of the s1d13705 11 gnd ground 12 gnd ground 13 sd8 connected to db8 of the s1d13705 14 sd9 connected to db9 of the s1d13705 15 sd10 connected to db10 of the s1d13705 16 sd11 connected to db11 of the s1d13705 17 gnd ground 18 gnd ground 19 sd12 connected to db12 of the s1d13705 20 sd13 connected to db13 of the s1d13705 21 sd14 connected to db14 of the s1d13705 22 sd15 connected to db15 of the s1d13705 23 reset# connected to the reset# signal of the s1d13705 24 gnd ground 25 gnd ground 26 gnd ground 27 +12v 12 volt supply 28 +12v 12 volt supply 29 we0# connected to the we0# signal of the s1d13705 30 wait# connected to the wait# signal of the s1d13705 31 cs# connected to the cs# signal of the s1d13705 32 nc not connected 33 we1# connected to the we1# signal of the s1d13705 34 iov dd connected to the iov dd supply of the s1d13705 4: cpu/bus interface connector pinouts s5u13705b00c rev. 1.0 isa bus evaluation epson 4-5 board user? manual (x27a-g-005-01) table 4-2 cpu/bus connector (h2) pinout connector pin no. cpu/bus pin name comments 1 sa0 connected to ab0 of the s1d13705 2 sa1 connected to ab1 of the s1d13705 3 sa2 connected to ab2 of the s1d13705 4 sa3 connected to ab3 of the s1d13705 5 sa4 connected to ab4 of the s1d13705 6 sa5 connected to ab5 of the s1d13705 7 sa6 connected to ab6 of the s1d13705 8 sa7 connected to ab7 of the s1d13705 9 gnd ground 10 gnd ground 11 sa8 connected to ab8 of the s1d13705 12 sa9 connected to ab9 of the s1d13705 13 sa10 connected to ab10 of the s1d13705 14 sa11 connected to ab11 of the s1d13705 15 sa12 connected to ab12 of the s1d13705 16 sa13 connected to ab13 of the s1d13705 17 gnd ground 18 gnd ground 19 sa14 connected to ab14 of the s1d13705 20 sa15 connected to ab15 of the s1d13705 21 sa16 connected to ab16 of the s1d13705 22 sa17 connected to sa17 of the isa bus connector 23 sa18 connected to sa18 of the isa bus connector 24 sa19 connected to sa19 of the isa bus connector 25 gnd ground 26 gnd ground 27 v cc 5 volt supply 28 v cc 5 volt supply 29 rd/wr# connected to the r/w# signal of the s1d13705 30 bs# connected to the bs# signal of the s1d13705 31 busclk connected to the bclk signal of the s1d13705 32 rd# connected to the rd# signal of the s1d13705 33 nc not connected 34 clki connected to the clki signal of the s1d13705 5: host bus interface pin mapping 4-6 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 5h ost b us i nterface p in m apping table 5-1 host bus interface pin mapping s1d13705 pin names sh-3 sh-4 mc68k #1 mc68k #2 generic bus #1 generic bus #2 ab[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] a[16:1] ab0 a0 a0 lds# a0 a0 a0 db[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] we1# we1# we1# uds# ds# we1# bhe# cs# csn# csn# external decode external decode external decode external decode bclk ckio ckio bclk bclk bclk bclk bs# bs# bs# as# as# connect to v ss connect to io v dd rd/wr# rd/wr# rd/wr# r/w# r/w# rd1# connect to io v dd rd# rd# rd# connect to io v dd siz1 rd0# rd# we0# we0# we0# connect to io v dd siz0 we0# we# wait# wait# rdy# dtack# dsack1# wait# wait# reset# reset# reset# reset# reset# reset# reset# 6: technical description s5u13705b00c rev. 1.0 isa bus evaluation epson 4-7 board user? manual (x27a-g-005-01) 6t echnical d escription 6.1 embedded memory support the s1d13705 contains 80k bytes of embedded, 16-bit, sram used for the display buffer and a 32 byte internal register set. since the s1d13705 does not distinguish between memory and register accesses, both the 80k byte display buffer and the 32 byte register set must be memory mapped into the host s memory space. when using the s5u13705b00c board on an isa bus system, the board can be con?ured to map the s1d13705 to one of two memory blocks. the sram start address is determined by a dip switch setting. see ?able 2-1 con?uration dip switch settings,?on page 4-2. 1. when switch s1-5 is in the closed position, the s1d13705 is mapped into segments 0c0000h and 0d0000h. this memory space is in the ?st 1m byte of isa bus memory and should be used if these segments are not taken up by other devices such as network adapters, scsi cards, or other peripherals. note: since vga and vga compatible video adapters use address 0c8000, these cards cannot be used while using the s5u13705b00c board at this memory address. a monochrome display adapter, a terminal, or a non-vga compatible display adapter must be used. 2. when switch s1-5 is in the open position, the s1d13705 is mapped into the upper megabyte of isa bus memory, starting address of f00000h. to use this memory on an isa bus system, the system bios has to be con?ured to set a memory ?ole starting at this address. some systems allow the user to con?ure the size of this hole and the starting address of where it begins while others just allow a 1m byte hole at the top of the 16m byte memory space. this memory hole is con?ured by entering the system cmos setup utility. this memory space should be used if segments 0dh and 0eh are being used by other devices or if a vga display adapter is needed. starting at the sram start address, the board design decodes a 128k byte segment accommodating both the 80k byte display buffer and the s1d13705 internal register set. the s1d13705 registers are mapped into the upper 32 bytes of the 128k byte segment (1ffe0h to 1ffffh). when using the s5u13705b00c board on a non-isa bus system, system or external decode logic must map the s1d13705 into an appropriate memory space. 6: technical description 4-8 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 6.2 isa bus support the s5u13705b00c board has been designed to directly support the 16-bit isa bus environment and can be used in conjunction with either a vga or a monochrome display adapter card. there are 4 con?uration inputs associated with the host interface (cnf[2:0] and bs#). refer to ?able 2-3 jumper settings,?on page 4-2 and ?able 5-1 host bus interface pin mapping,?on page 4-6 for complete details. display adapter card support when using the s5u13705b00c in conjunction with another primary display adapter (vga or monochrome) the following applies: vga display adapter all vga display adapters can be used with the s5u13705b00c board if the s1d13705 is mapped to the upper 1m byte of isa bus memory, address f00000-f1ffff. if the s1d13705 is mapped to the address range 0c0000-0d0000, then no vga or vga compatible display adapters can be used with the s5u13705b00c board. see ?.1 embedded memory support?on page 4-7. monochrome display adapter the s5u13705b00c board can be used with monochrome display adapters at both memory addresses. expanded memory manager support if a memory manager is being used for system memory, the address range selected for the sram start address must be excluded from use or memory con?cts will arise. 6.3 non-isa bus support the s5u13705b00c board is speci?ally designed to support the standard 16-bit isa bus. however, the s1d13705 directly supports many other host bus interfaces. header strips h1 and h2 are provided and contain all the necessary io pins to interface to these host buses. see ? cpu/bus interface connector pinouts?on page 4-4; ?able 2-1 con?uration dip switch settings,?on page 4-2; and ?able 2-3 jumper settings,?on page 4-2 for details. when using the header strips to provide the bus interface observe the following: all signals on the isa bus card edge must be isolated from the isa bus (do not plug the card into a computer). power must be provided through the headers. u7, a pld of type 22v10-15, is used to provide the s1d13705 cs# (pin 74) and other decoding logic signals for isa bus mode. for non-isa applications, this functionality must be provided externally. remove the pal from its socket to eliminate con?cts driving s1d13705 control sig- nals. refer to table 5-1 for connection details. note: when using a 3.3v host bus interface, io v dd must be set to 3.3v by setting jumper (jp1) to the 2-3 position. refer to ?able 2-3 jumper settings,?on page 4-2. 6: technical description s5u13705b00c rev. 1.0 isa bus evaluation epson 4-9 board user? manual (x27a-g-005-01) 6.4 decoding logic all the required decode logic is provided through a pld of type 22v10-15 (u7, socketed). this pal contains the following equations. !cs = (address >= ^hc0000) & (address <= ^hdffff) & !addr & refresh & enab # (address1 >= ^hf00000) & (address1 <= ^hf1ffff) & addr & refresh & enab; !memcs16 = (address1 >= ^h0c0000) & (address1 <= ^h0dffff) & !addr & !cs # (address1 >= ^hf00000) & (address1 <= ^hf1ffff) & addr & !cs; !we0 = (!cs & !addr & !smemw) # (!cs & addr & !memw); !rd = (!cs & !addr & !smemr) # (!cs & addr & !memr); note: addr = switch s1-5 (see table 2-1, ?onfiguration dip switch settings,?on page 1-2). 6.5 clock input support the input clock (clki) frequency can be up to 50mhz for the s1d13705 if the internal clock divide-by-2 mode is set. if the clock divider is not used, the maximum clki frequency is 25mhz. there is no minimum input clock frequency. a 25.0mhz oscillator (u2, socketed) is provided as the input clock source. however, depending on the lcd resolution , desired frame rate, and power consumtion budget, a lower frequency clock may be required. 6.6 lcd panel voltage setting the s5u13705b00c board supports both 3.3v and 5v lcd panels through the lcd connector j5. the voltage level is selected by setting jumper j4 to the appropriate position. refer to ?able 2-3 jumper settings,?on page 4-2 for setting this jumper. although not necessary for signal buffering, buffers have been implemented in the board design to provide ?xibility in handling 3 and 5 volt panels. 6.7 monochrome lcd panel support the s1d13705 directly supports 4 and 8-bit, dual and single, monochrome passive lcd panels. all necessary signals are provided on the 40-pin ribbon cable header j5. the interface signals on the cable are alternated with grounds to reduce crosstalk and noise. refer to ?able 3-1 lcd signal connector (j5) pinout,?on page 4-3 for speci? connection information. 6.8 color passive lcd panel support the s1d13705 directly supports 4 and 8-bit, dual and single, color passive lcd panels. all the necessary signals are provided on the 40-pin ribbon cable header j5. the interface signals on the cable are alternated with grounds to reduce crosstalk and noise. refer to ?able 3-1 lcd signal connector (j5) pinout,?on page 4-3 for speci? connection information. 6: technical description 4-10 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 6.9 color tft/d-tfd lcd panel support the s1d13705 directly supports 9 and 12-bit active matrix color tft/d-tfd panels. all the necessary signals can also be found on the 40-pin lcd connector j5. the interface signals on the cable are alternated with grounds to reduce crosstalk and noise. refer to ?able 3-1 lcd signal connector (j5) pinout,?on page 4-3 for connection information. 6.10 power save modes the s1d13705 supports hardware and software power save modes. these modes are controlled by the utility 1375pwr. the hardware power save mode needs to be enabled by 1375pwr and then activated by dip switch s1-6. see ?able 2-1 con?uration dip switch settings,?on page 4-2 for details on setting this switch. 6.11 adjustable lcd panel negative power supply for those lcd panels requiring a negative power supply to provide between -23v and -14v (i out =25ma) a power supply has been provided as an integral part of this design. the vlcd power supply can be adjusted by r21 to give an output voltage from -23v to -14v, and is enabled and disabled by the active high s1d13705 control signal lcdpwr, inverted externally. determine the panel s speci? power requirements and set the potentiometer accordingly before connecting the panel. 6.12 adjustable lcd panel positive power supply for those lcd panels requiring a positive power supply to provide between +23v and +40v (i out =45ma) a power supply has been provided as an integral part of this design. the vddh power supply can be adjusted by r15 to provide an output voltage from +23v to +40v and is enabled and disabled by the active high s1d13705 control signal lcdpwr, inverted externally. determine the panel s speci? power requirements and set the potentiometer accordingly before connecting the panel. 6.13 cpu/bus interface header strips all of the cpu/bus interface pins of the s1d13705 are connected to the header strips h1 and h2 for easy interface to a cpu/bus other than isa. refer to ?able 4-1 cpu/bus connector (h1) pinout,?on page 4-4 and ?able 4-2 cpu/bus connector (h2) pinout,?on page 4-5 for speci? settings. note: these headers only provide the cpu/bus interface signals from the s1d13705. when another host bus interface is selected by cnf[3:0] and bs#, appropriate external decoding logic must be used to access the s1d13705. refer to ?able 5-1 host bus interface pin mapping,?on page 4-6 for connection details. 7: parts list s5u13705b00c rev. 1.0 isa bus evaluation epson 4-11 board user? manual (x27a-g-005-01) 7p arts l ist item # qty/board designation part value description 1 15 c1-c11, c15-17,c24 0.1uf, 20%, 50v 0805 ceramic capacitor 2 3 c12-14 10uf, 10%, 25v tantalum capacitor size d 3 2 c18, c22 47uf, 10%, 16v tantalum capacitor size d 4 3 c19-c21 4.7uf, 10%, 50v tantalum capacitor size d 5 1 c23 56uf, 20%, 63v electrolytic, radial, low esr 6 2 h1,h2 con34a header 0.1?17x2 header, pth 7 5 jp1-jp4, jp6 header 3 0.1?1x3 header, pth 8 1 j1 at con-a isa bus gold ?gers 9 1 j2 at con-b isa bus gold ?gers 10 1 j3 at con-c isa bus gold ?gers 11 1 j4 at con-d isa bus gold ?gers 12 1 j5 con40a shrouded header 2x20, pth, center key 13 1 l1 1? mci-1812 inductor 14 2 l3, l4 ferrite bead philips bds3/3/8.9-4s2 15 1 q1 2n3906 pnp signal transistor, sot23 16 1 q2 2n3904 npn signal transistor, sot23 17 6 r1-r6 15k, 5% 0805 resistor 18 9 r7-r13, r17, r18 10k, 5% 0805 resistor 19 1 r14 475k, 1% 0805 resistor 20 1 r15 200k pot. 200k trim pot spectrol 63s204t607 (or equivalent) 21 1 r16 14k, 1% 0805 resistor 22 3 r19, r20, r22 100k, 5% 0805 resistor 23 1 r21 100k pot. 100k trim pot spectrol 63s104t607 (or equivalent) 24 1 s1 sw dip-6 6 position dip switch 25 1 u1 s1d13705f00a qfp14-80, 80 pin, smt 26 1 u2 25.0 mhz oscillator fox 25mhz oscillator or equiv., 14 pin dip socketed 27 3 u3-u5 74ahc244 so-22, ti74ahc244 28 1 u6 lt1117cm-3.3 linear technology 5v to 3.3v regulator, 800ma 29 1 u7 pld22v10-15 pld type 22v10-15, 20 pin dip, socketed 30 1 u8 74als125 so-14, 74als125 31 1 u9 74hct04 so-14, 74hct04 32 1 u10 rd-0412 xentek rd-0412, positive ps 33 1 u11 epn001 xentek epn001 negative ps 8: schematic diagrams 4-12 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) 8s chematic d iagrams figure 8-1 s5u13705b00c schematic diagram (1 of 4) 3 c d 8 7 6 5 4 2 1 d c b a 1 2 3 4 5 6 7 8 b a by-pass capacitors (1 per power pin) 1 2 5.0v iovdd 2 3 3.3v iovdd 1.0 epson research & development, inc. s5u13705b00c isa-bus rev. 1. 0 evaluation board : 13705f00a chip b 14 monday, january 04, 1999 size document number rev date: sheet of fpdat2 sd2 fpdat4 sd11 sd4 sa3 sd13 sd5 fpdat[0..7] sd6 sa15 sd8 sa7 fpdat0 sd10 sd7 sd1 sa[0..19] sd[0..15] sd12 sd3 sa2 sa5 sd14 sa13 sa1 fpdat3 sa4 sa0 sd15 sa10 sa9 sa8 fpdat1 sd9 sd0 sa14 sa12 sa11 sa6 fpdat5 fpdat6 fpdat7 cnf2 cnf1 cnf2 cnf0 cnf3 cnf3 cnf[0..3] cnf1 cnf0 sa16 3.3v iovdd 3.3v iovdd iovdd iovdd iovdd vcc c1 0.1uf c6 0.1uf c7 0.1uf c5 0.1uf jp2 header 3 1 2 3 jp3 header 3 1 2 3 r4 15k r3 15k r2 15k r1 15k r5 15k c2 0.1uf c4 0.1uf c3 0.1uf jp1 header 3 1 2 3 r6 15k s1 sw dip-6 1 2 3 4 5 6 12 11 10 9 8 7 u1 s1d13705f00a ab0 70 ab1 69 ab2 68 ab3 67 ab4 66 ab5 65 ab6 64 ab7 63 ab8 62 ab9 59 ab10 58 ab11 57 ab12 56 ab13 55 ab14 54 ab15 53 fpdat0 37 fpdat1 36 fpdat2 35 fpdat3 34 fpdat5 32 fpdat6 31 fpdat7 30 cs# 74 lcdpwr 43 corevdd 61 vss 20 vss 40 vss 72 vss 60 vss 50 vss 27 vss 80 db0 19 db1 18 db2 17 db3 16 db4 15 db5 14 db6 13 db7 12 db8 11 db9 9 db10 8 db11 7 db12 6 db13 5 db14 4 db15 3 fpdat4 33 cnf0 49 cnf1 48 cnf2 47 cnf3 46 ab16 45 rd/wr# 79 we1# 78 we0# 77 rd# 76 bs# 75 reset# 73 clki 51 bclk 71 wait# 2 teste n 44 corevdd 1 corevdd 21 iovdd 10 corevdd 41 iovdd 52 iovdd 29 fpdat8/gpio1 26 fpdat9gpio2 25 fpdat10/gpio3 24 fpdat11/gpio4 23 fpframe 39 fpline 38 fpshift 28 drdy 42 gpio0 22 sd[0..15] lcdpwr drdy fpframe fpline fpshift fpdat[0..7] rd/wr# we1# we0# cs# busclk clki reset# rd# wait# bs# sa[0..19] fpdat8 fpdat9 fpdat10 fpdat11 cnf[0..3] suspend bs# rd/wr# cnf[0..3] suspend addr 8: schematic diagrams s5u13705b00c rev. 1.0 isa bus evaluation epson 4-13 board user? manual (x27a-g-005-01) figure 8-2 s5u13705b00c schematic diagram (2 of 4) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 a a b b c c d d memcs16 1.0 epson research & development, inc. s5u13705b00c isa-bus rev. 1.0 evaluation board : isa-bus and pal decode b 24 monday, january 04, 1999 size document number rev date: sheet of sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 sd[0..15] sa[0..19] sa9 sa10 la21 sa14 sa17 sa8 sa15 sa0 sa4 sa13 la23 la[17..23] sa19 la19 la18 sa7 sa3 la20 sa16 sa6 sa2 sa11 sa12 la22 la17 sa1 sa18 sa5 la[17..23] sa[0..19] la23 la22 la21 la20 la19 la18 la17 sa19 sa18 sa17 sa16 iovdd vcc iovdd vcc +12v iovdd iovdd vcc vcc vcc iovdd vcc j1 at con-a /iochck 1 sd7 2 sd6 3 sd5 4 sd4 5 sd3 6 sd2 7 sd1 8 sd0 9 iochrdy 10 aen 11 sa19 12 sa18 13 sa17 14 sa16 15 sa15 16 sa14 17 sa13 18 sa12 19 sa11 20 sa10 21 sa9 22 sa8 23 sa7 24 sa6 25 sa5 26 sa4 27 sa3 28 sa2 29 sa1 30 sa0 31 j2 at con-b gnd 1 reset 2 +5v 3 irq9 4 -5v 5 drq2 6 -12v 7 ows 8 +12v 9 gnd 10 /smemw 11 /smemr 12 /iow 13 /ior 14 /dack3 15 drq3 16 /dack1 17 drq1 18 /refresh 19 clk 20 irq7 21 irq6 22 irq5 23 irq4 24 irq3 25 /dack2 26 t/c 27 bale 28 +5v 29 osc 30 gnd 31 j4 at con-d /memcs16 1 /iocs16 2 irq10 3 irq11 4 irq12 5 irq15 6 irq14 7 /dack0 8 drq0 9 /dack5 10 drq5 11 /dack6 12 drq6 13 /dack7 14 drq7 15 +5v 16 master 17 gnd 18 + c14 10uf/25v r7 10k + c13 10uf/25v j3 at con-c /sbhe 1 la23 2 la22 3 la21 4 la20 5 la19 6 la18 7 la17 8 /memr 9 /memw 10 sd8 11 sd9 12 sd10 13 sd11 14 sd12 15 sd13 16 sd14 17 sd15 18 r9 10k r10 10k r12 10k u8a 74ls125 2 3 14 1 7 c16 0.1uf r8 10k u7 tibpal22v10 clk/in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 in 9 in 10 in 11 gnd 12 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 in 13 vcc 24 c15 0.1uf r11 10k r13 10k c17 0.1uf u9a 74hct04 1 2 14 7 r22 100k refresh# reset memcs16# we1# sd[0..15] sa[0..19] la[17..23] wait# busclk smemw# smemr# cs# reset# reset refresh# memcs16# memw# memr# la[17..23] sa[0..19] addr memr# memw# smemr# smemw# rd# we0# 8: schematic diagrams 4-14 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) figure 8-3 s5u13705b00c schematic diagram (3 of 4) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 a a b b c c d d selectable 3.3v / 5.0v color/mono lcd connector 1 2 5.0v lcd panels 2 3 3.3v lcd panels 1.0 epson research & development, inc. s5u13705b00c isa-bus rev. 1.0 evaluation card : lcd connector & headers b 34 monday, january 04, 1999 size document number rev date: sheet of fpdat[0..7] bfpdat0 bfpdat1 bfpdat2 bfpdat3 bfpdat4 bfpdat5 bfpdat6 bfpdat7 bfpdat8 bfpdat9 bfpdat10 bfpdat11 fpdat0 fpdat1 fpdat2 fpdat3 fpdat4 fpdat5 fpdat6 fpdat7 fpdat8 fpdat9 fpdat10 fpdat11 sa[0..19] sa1 sa3 sa9 sa11 sa13 sa15 sa17 sa19 sa0 sa2 sa4 sa6 sa8 sa10 sa12 sa14 sa16 sa18 sa5 sa7 sd14 sd9 sd13 sd12 sd7 sd11 sd10 sd8 sd5 sd3 sd6 sd4 sd1 sd[0..15] sd2 sd0 sd15 fpshift lcdvcc lcdvcc fpframe blcdpwr drdy bdrdy fpline bfpframe bfpshift bfpline lcdp +12v vddh vlcd vcc vcc vcc vcc +12v +12v 3.3v vcc iovdd j5 con40a 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 u3 74ahc244 1a1 2 1y1 18 1a2 4 1y2 16 1a3 6 1y3 14 1a4 8 1y4 12 2a1 11 2y1 9 2a2 13 2y2 7 2a3 15 2y3 5 2a4 17 2y4 3 1g 1 2g 19 vcc 20 gnd 10 u4 74ahc244 1a1 2 1y1 18 1a2 4 1y2 16 1a3 6 1y3 14 1a4 8 1y4 12 2a1 11 2y1 9 2a2 13 2y2 7 2a3 15 2y3 5 2a4 17 2y4 3 1g 1 2g 19 vcc 20 gnd 10 c8 0.1uf c9 0.1uf jp4 header 3 1 2 3 + c12 10uf/25v u6 lt1117cm-3.3 vin 3 adj 1 vout 2 c11 0.1uf h1 header 17x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 h2 header 17x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 c10 0.1uf u5 74ahc244 1a1 2 1y1 18 1a2 4 1y2 16 1a3 6 1y3 14 1a4 8 1y4 12 2a1 11 2y1 9 2a2 13 2y2 7 2a3 15 2y3 5 2a4 17 2y4 3 1g 1 2g 19 vcc 20 gnd 10 u2 25.0mhz nc 1 out 8 gnd 7 vcc 14 c24 0.1uf jp6 header 3 1 2 3 fpshift drdy fpline fpframe fpdat[0..7] fpdat8 fpdat9 fpdat10 fpdat11 bs# rd# wait# we0# cs# reset# we1# sa[0..19] sd[0..15] rd/wr# busclk clki clki lcdpwr lcdpwr# 8: schematic diagrams s5u13705b00c rev. 1.0 isa bus evaluation epson 4-15 board user? manual (x27a-g-005-01) figure 8-4 s5u13705b00c schematic diagram (4 of 4) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 a a b b c c d d 1.0 epson research & development, inc. s5u13705b00c isa-bus rev. 1.0 evaluation board : lcd power supply b 44 monday, january 04, 1999 size document number rev date: sheet of lcdpwr# psvcc psvcc vcc psvcc psvcc iovdd vlcd vddh vcc vcc vcc vcc vcc + c21 4.7uf/50v r18 10k r19 100k r20 100k r14 475k r15 200k pot. 1 3 2 r16 14k + c19 4.7uf/50v + c20 4.7uf/50v + c22 47uf/16v + c23 56uf/35v low esr + c18 47uf/16v r17 10k r21 100k pot. 1 3 2 u10 rd-0412 vout_adj 1 dc_in 2 remote 3 gnd 4 gnd 5 gnd 6 gnd 7 gnd 8 nc 9 gnd 10 gnd 11 dc_out 12 u11 epn001 dc_out 1 dc_out 2 nc 3 gnd 4 gnd 5 vout_adj 6 nc 7 nc 8 nc 9 dc_in 11 dc_in 10 l1 1uh 2 5 l3 1 2 l4 1 2 u9b 74hct04 3 4 14 7 q2 mmbt3904 1 2 3 q1 mmbt3906 1 2 3 u9c 74hct04 5 6 14 7 u9d 74hct04 9 8 14 7 u9e 74hct04 11 10 14 7 u9f 74hct04 13 12 14 7 psgnd psgnd psgnd lcdpwr lcdpwr# 8: schematic diagrams 4-16 epson s5u13705b00c rev. 1.0 isa bus evaluation board user? manual (x27a-g-005-01) this page is blank. s1d13705f00a embedded memory lcd controller application notes contents s1d13705f00a application notes epson 5-i contents 1i nterfacing to the m otorola mc68328 ? ragonball ?m icroprocessor ..........................5-1 1.1 introduction................................................................................................................ ....................5-1 1.2 interfacing to the mc68328 .................................................................................................. .........5-1 the mc68328 system bus ........................................................................................................5 -1 chip-select module............................................................................................................. .......5-2 1.3 s1d13705 host bus interface ................................................................................................. ......5-2 host bus pin connection ........................................................................................................ ...5-2 generic #1 interface mode ...................................................................................................... ..5-3 mc68k #1 interface mode ........................................................................................................ .5-4 1.4 mc68328 to s1d13705 interface............................................................................................... ..5-5 hardware description ........................................................................................................... .....5-5 s1d13705 hardware configuration ...........................................................................................5-7 mc68328 chip select configuration..........................................................................................5-7 1.5 software .................................................................................................................... ....................5-7 2i nterfacing to the m otorola mpc821 m icroprocessor ....................................................5-8 2.1 introduction................................................................................................................ ....................5-8 2.2 interfacing to the mpc821................................................................................................... ..........5-8 the mpc8xx system bus .......................................................................................................... 5-8 mpc821 bus overview ............................................................................................................ ..5-8 memory controller module....................................................................................................... 5-11 2.3 s1d13705 host bus interface ................................................................................................. ....5-11 host bus interface modes....................................................................................................... .5-12 generic #1 host bus interface mode .......................................................................................5-12 2.4 mpc821 to s1d13705 interface ................................................................................................ .5-13 hardware description ........................................................................................................... ...5-13 mpc821ads evaluation board hardware connections..........................................................5-14 s1d13705 hardware configuration .........................................................................................5-15 mpc821 chip select configuration .........................................................................................5-16 test software .................................................................................................................. .........5-17 2.5 software .................................................................................................................... ..................5-17 3i nterfacing to the m otorola mcf5307 ? old f ire ?m icroprocessor ............................5-18 3.1 introduction................................................................................................................ ..................5-18 3.2 interfacing to the mcf5307 .................................................................................................. .......5-18 the mcf5307 system bus ......................................................................................................5-1 8 chip-select module............................................................................................................. .....5-20 3.3 s1d13705 bus interface ...................................................................................................... .......5-20 host bus pin connection ........................................................................................................ .5-20 generic #1 interface mode ...................................................................................................... 5-21 3.4 mcf5307 to s1d13705 interface ..............................................................................................5 -21 hardware description ........................................................................................................... ...5-21 s1d13705 hardware configuration .........................................................................................5-22 mcf5307 chip select configuration .......................................................................................5-23 3.5 software .................................................................................................................... ..................5-23 4i nterfacing to the pc c ard b us .......................................................................................5-24 4.1 introduction................................................................................................................ ..................5-24 4.2 interfacing to the pc card bus.............................................................................................. ......5-24 the pc card system bus ........................................................................................................5 -24 4.3 s1d13705 bus interface ...................................................................................................... .......5-26 host bus pin connection ........................................................................................................ .5-26 generic #2 interface mode ...................................................................................................... 5-26 4.4 pc card to s1d13705 interface............................................................................................... ...5-27 hardware connections ........................................................................................................... .5-27 s1d13705 hardware configuration .........................................................................................5-28 register/memory mapping .......................................................................................................5 -28 contents 5-ii epson s1d13705f00a application notes 4.5 software .................................................................................................................... .................. 5-28 5i nterfacing to the t oshiba mips tmpr3912 m icroprocessor ........................................5-29 5.1 introduction ................................................................................................................ ................. 5-29 5.2 interfacing to the tmpr3912 ................................................................................................. ..... 5-29 5.3 s1d13705 host bus interface................................................................................................. .... 5-29 host bus pin connection........................................................................................................ . 5-29 generic #1 interface mode ...................................................................................................... 5-30 generic #2 interface mode ...................................................................................................... 5-31 5.4 direct connection to the toshiba tmpr3912............................................................................. 5-31 general description ............................................................................................................ ..... 5-31 memory mapping and aliasing ................................................................................................ 5-32 s1d13705 configuration ......................................................................................................... 5-33 5.5 using the ite it8368e pc card buffer ...................................................................................... 5- 33 hardware description ........................................................................................................... ... 5-33 it8368e configuration.......................................................................................................... ... 5-34 memory mapping and aliasing ................................................................................................ 5-35 s1d13705 configuration ......................................................................................................... 5-35 5.6 software .................................................................................................................... .................. 5-35 6i nterfacing to the p hilips mips pr31500/pr31700 p rocessor ......................................5-36 6.1 introduction ................................................................................................................ ................. 5-36 6.2 interfacing to the pr31500/pr31700 ......................................................................................... 5 -36 6.3 s1d13705 host bus interface................................................................................................. .... 5-36 host bus pin connection........................................................................................................ . 5-37 generic #1 interface mode ...................................................................................................... 5-37 generic #2 interface mode ...................................................................................................... 5-38 6.4 direct connection to the philips pr31500/pr31700 .................................................................. 5-39 general description ............................................................................................................ ..... 5-39 memory mapping and aliasing ................................................................................................ 5-40 s1d13705 configuration and pin mapping ............................................................................. 5-40 6.5 using the ite it8368e pc card buffer ...................................................................................... 5- 40 hardware description ........................................................................................................... ... 5-40 it8368e configuration.......................................................................................................... ... 5-42 memory mapping and aliasing ................................................................................................ 5-42 s1d13705 configuration ......................................................................................................... 5-42 6.6 software .................................................................................................................... .................. 5-43 7i nterfacing to the nec vr4102/vr4111 m icroprocessor ..............................................5-44 7.1 introduction ................................................................................................................ ................. 5-44 7.2 interfacing to the nec vr4102/vr4111..................................................................................... 5-4 4 the nec vr4102/vr4111 system bus.................................................................................. 5-44 7.3 s1d13705 host bus interface................................................................................................. .... 5-46 host bus pin connection........................................................................................................ . 5-46 generic #2 interface mode ...................................................................................................... 5-46 7.4 vr4102/vr4111 to s1d13705 interface .................................................................................... 5-47 hardware description ........................................................................................................... ... 5-47 s1d13705 hardware configuration......................................................................................... 5-48 nec vr4102/vr4111 configuration....................................................................................... 5-48 7.5 software .................................................................................................................... .................. 5-48 8i nterfacing to the nec vr4181atm m icroprocessor ....................................................5-49 8.1 introduction ................................................................................................................ ................. 5-49 8.2 interfacing to the nec vr4181a .............................................................................................. .. 5-49 the nec vr4181a system bus ............................................................................................. 5-49 8.3 s1d13705 host bus interface................................................................................................. .... 5-50 host bus pin connection........................................................................................................ . 5-50 generic #2 interface mode ...................................................................................................... 5-50 8.4 vr4181a to s1d13705 interface............................................................................................... . 5-51 contents s1d13705f00a application notes epson 5-iii hardware description ........................................................................................................... ...5-51 s1d13705 hardware configuration .........................................................................................5-52 nec vr4181a configuration...................................................................................................5-5 2 8.5 software .................................................................................................................... ..................5-53 9 s1d13705 p ower c onsumption .........................................................................................5-54 9.1 s1d13705 power consumption .................................................................................................. 5-54 conditions ..................................................................................................................... ...........5-55 9.2 summary ..................................................................................................................... ................5-55 contents 5-iv epson s1d13705f00a application notes list of figures figure 1-1 typical implementation of mc68328 to s1d13705 interface - mc68k #1 .......................... 5-5 figure 1-2 typical implementation of mc68328 to s1d13705 interface - generic #1.......................... 5-6 figure 2-1 power pc memory read cycle ........................................................................................... 5-9 figure 2-2 power pc memory write cycle.......................................................................................... 5-10 figure 2-3 typical implementation of mpc821 to s1d13705 interface .............................................. 5-13 figure 3-1 mcf5307 memory read cycle.......................................................................................... 5- 19 figure 3-2 mcf5307 memory write cycle .......................................................................................... 5 -19 figure 3-3 typical implementation of mcf5307 to s1d13705 interface ............................................ 5-22 figure 4-1 pc card read cycle................................................................................................... ....... 5-25 figure 4-2 pc card write cycle .................................................................................................. ........ 5-25 figure 4-3 typical implementation of pc card to s1d13705 interface .............................................. 5-27 figure 5-1 s1d13705 to tmpr3912 direct connection ..................................................................... 5-32 figure 5-2 s1d13705 to tmpr3912 connection using an it8368e .................................................. 5-34 figure 6-1 s1d13705 to pr31500/pr31700 direct connection ........................................................ 5-39 figure 6-2 s1d13705 to pr31500/pr31700 connection using an it8368e ..................................... 5-41 figure 7-1 nec vr4102/vr4111 read/write cycles......................................................................... 5-45 figure 7-2 typical implementation of vr4102/vr4111 to s1d13705 interface ................................. 5-47 figure 8-1 typical implementation of vr4181a to s1d13705 interface............................................. 5-51 list of tables table 1-1 host bus interface pin mapping ........................................................................................ .. 5-2 table 1-2 summary of power-on/reset options................................................................................. 5-7 table 1-3 host bus interface selection.......................................................................................... ...... 5-7 table 2-1 host bus interface pin mapping ........................................................................................ 5-12 table 2-2 list of connections from mpc821ads to s1d13705 ....................................................... 5-14 table 2-3 configuration settings................................................................................................ ........ 5-15 table 2-4 host bus interface selection.......................................................................................... .... 5-15 table 3-1 host bus interface pin mapping ........................................................................................ 5-20 table 3-2 summary of power-on/reset options............................................................................... 5-22 table 3-3 host bus interface selection.......................................................................................... .... 5-22 table 4-1 host bus interface pin mapping ........................................................................................ 5-26 table 4-2 summary of power-on/reset options............................................................................... 5-28 table 4-3 host bus interface selection.......................................................................................... .... 5-28 table 5-1 host bus interface pin mapping ........................................................................................ 5-29 table 5-2 s1d13705 configuration for direct connection ................................................................. 5-33 table 5-3 tmpr3912 to pc card slots address mapping with and without the it8368e ............... 5-35 table 5-4 s1d13705 configuration using the it8368e ..................................................................... 5-35 table 6-1 host bus interface pin mapping ........................................................................................ 5-37 table 6-2 s1d13705 configuration for direct connection ................................................................. 5-40 table 6-3 pr31500/pr31700 to pc card slots address mapping with and without the it8368e .. 5-42 table 6-4 s1d13705 configuration using the it8368e ..................................................................... 5-42 table 7-1 host bus interface pin mapping ........................................................................................ 5-46 table 7-2 summary of power-on/reset options............................................................................... 5-48 table 7-3 host bus interface selection.......................................................................................... .... 5-48 table 8-1 host bus interface pin mapping ........................................................................................ 5-50 table 8-2 summary of power-on/reset options............................................................................... 5-52 table 8-3 host bus interface selection.......................................................................................... .... 5-52 table 9-1 s1d13705 total power consumption................................................................................ 5-55 1: interfacing to the motorola mc68328 ?ragonball?microprocessor s1d13705f00a application notes epson 5-1 (x27a-g-007-01) 1i nterfacing to the m otorola mc68328 ? ragonball ?m icroprocessor 1.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the motorola mc68328 ?ragonball?microprocessor. by implementing an embedded display refresh buffer, the s1d13705 can reduce system power consumption, improve image quality, and increase system performance as compared to the dragonball s on-chip lcd controller. 1.2 interfacing to the mc68328 the mc68328 system bus the mc68328 is an integrated controller for handheld products, based upon the mc68ec000 microprocessor core. it implements a 16-bit data bus and a 32-bit address bus. the bus interface consists of all the standard mc68000 bus interface signals, plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices. the mc68000 bus control signals are well documented in motorola s user manuals, and will not be described here. a brief summary of the new signals appears below: output enable (oe#) is asserted when a read cycle is in process; it is intended to connect to the output enable control of a typical static ram, eprom, or flash eprom device. upper write enable and lower write enable (uwe#/lwe#) are asserted during memory write cycles for the upper and lower bytes of the 16-bit data bus; they may be directly connected to the write enable inputs of a typical memory device. the s1d13705 implements the mc68000 bus interface using its mc68k #1 mode, so this mode may be used to connect the mc68328 directly to the s1d13705 with no glue logic. however, several of the mc68000 bus control signals are multiplexed with io and interrupt signals on the mc68328, and in many applications it may be desirable to make these pins available for these alternate functions. this requirement may be accommodated through the use of the generic #1 interface mode on the s1d13705. x27a-g-007-01 1: interfacing to the motorola mc68328 ?ragonball?microprocessor 5-2 epson s1d13705f00a application notes (x27a-g-007-01) chip-select module the mc68328 can generate up to 16 chip select outputs, organized into four groups a?through ?? each chip select group has a common base address register and address mask register, to set the base address and block size of the entire group. in addition, each chip select within a group has its own address compare and address mask register, to activate the chip select for a subset of the group s address block. finally, each chip select may be individually programmed to control an 8 or 16-bit device, and each may be individually programmed to generate from 0 through 6 wait states internally, or allow the memory or peripheral device to terminate the cycle externally through use of the standard mc68000 dtack# signal. groups a and b can have a minimum block size of 64k bytes, so these are typically used to control memory devices. chip select a0 is active immediately after reset, so it is typically used to control a boot eprom device. groups c and d have a minimum block size of 4k bytes, so they are well- suited to controlling peripheral devices. chip select d3 is associated with the mc68328 on-chip pcmcia control logic. 1.3 s1d13705 host bus interface this section is a summary of the host bus interface modes available on the s1d13705 that may be used to interface to the mc68328. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the two interface modes that may be used for the mc68328 are: motorola mc68k #1 (using upper data strobe/lower data strobe). generic #1 (chip select, plus individual read enable/write enable for each byte). host bus pin connection the following table shows the functions of each host bus interface signal. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-01. table 1-1 host bus interface pin mapping s1d13705 pin names mc68k #1 generic #1 ab[15:1] a[15:1] a[15:1] ab0 lds# a0 db[15:0] d[15:0] d[15:0] we1# uds# we1# cs# external decode external decode bclk clk bclk bs# as# connect to v ss rd/wr# r/w# rd1# rd# connect to io v dd rd0# we0# connect to io v dd we0# wait# dtack# wait# reset# reset# reset# 1: interfacing to the motorola mc68328 ?ragonball?microprocessor s1d13705f00a application notes epson 5-3 (x27a-g-007-01) generic #1 interface mode generic #1 interface mode is the most general and least processor-speci? interface mode on the s1d13705. the generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. the interface requires the following signals: busclk is a clock input which is required by the s1d13705 host interface. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we0# and we1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is writing data to the s1d13705. these signals must be generated by external hardware based on the control outputs from the host cpu. rd# and rd/wr# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading data from the s1d13705. these signals must be gener- ated by external hardware based on the control outputs from the host cpu. wait# is a signal output from the s1d13705 that indicates the host cpu must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) signal is not used in the bus interface for generic #1 mode. however, bs# is used to con?ure the s1d13705 for generic #1 mode and should be tied low (connected to gnd). 1: interfacing to the motorola mc68328 ?ragonball?microprocessor 5-4 epson s1d13705f00a application notes (x27a-g-007-01) mc68k #1 interface mode the mc68k #1 interface mode can be used to interface to the mc68328 microprocessor if the previously mentioned, multiplexed, bus signals will not be used for other purposes. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab1 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. a0 and we1# are the enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading or writing data to the s1d13705. rd/wr# is the read/write signal that is driven low when the cpu writes to the s1d13705 and is driven high when the cpu is doing a read from the s1d13705. wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. the bus status (bs#) signal indicates that the address on the address bus is valid. the we0# and rd# signals is not used in the bus interface for mc68k #1 and must be tied high (tied to io v dd ). 1: interfacing to the motorola mc68328 ?ragonball?microprocessor s1d13705f00a application notes epson 5-5 (x27a-g-007-01) 1.4 mc68328 to s1d13705 interface hardware description the interface between the mc68328 and the s1d13705 can be implemented using either the mc68k #1 or generic #1 host bus interface of the s1d13705. using the mc68k #1 host bus interface the mc68328 multiplexes dual functions on some of its bus control pins (speci?ally uds#, lds#, and dtack#). in implementations where all of these pins are available for use as bus control pins, then the s1d13705 interface is a straightforward implementation of the ?c68k #1?host bus interface. for further information on this host bus interface, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. the following diagram shows a typical implementation of the mc68328 to s1d13705 using the mc68k #1 host bus interface. figure 1-1 typical implementation of mc68328 to s1d13705 interface - mc68k #1 mc68328 s1d13705 a[16:0] d[15:0] dtack# uds# lds# r/w# clk0 ab[16:1] db[15:0] cs# wait# we1# ab0 rd/wr# rd# busclk reset# vcc 470 csb3 as# bs# vcc system reset we0## vcc note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 1: interfacing to the motorola mc68328 ?ragonball?microprocessor 5-6 epson s1d13705f00a application notes (x27a-g-007-01) using the generic #1 host bus interface if uds# and/or lds# are required for their alternate io functions, then the mc68328 to s1d13705 interface may be implemented using the s1d13705 generic #1 host bus interface. note that in either case, the dtack# signal must be made available for the s1d13705, since it inserts a variable number of wait states depending upon cpu/lcd synchronization and the lcd panel display mode. wait# must be inverted (using an inverter enabled by cs#) to make it an active high signal and thus compatible with the mc68328 architecture. a single resistor is used to speed up the rise time of the wait# (dtack#) signal when terminating the bus cycle. the following diagram shows a typical implementation of the mc68328 to s1d13705 using the generic #1 host bus interface. figure 1-2 typical implementation of mc68328 to s1d13705 interface - generic #1 mc68328 s1d13705 a[16:0] d[15:0] dtack# uwe# lwe# oe# clk0 ab[16:0] db[15:0] cs# wait# we1# we0# rd/wr# rd# busclk reset# vcc 470 csb3 bs# note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). system reset 1: interfacing to the motorola mc68328 ?ragonball?microprocessor s1d13705f00a application notes epson 5-7 (x27a-g-007-01) s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02 for details. the tables below show those con?uration settings important to the mc68k #1 and generic #1 host bus interfaces. mc68328 chip select con?uration the s1d13705 requires a 128k byte address space for the display buffer and its internal registers. to accommodate this block size, it is preferable (but not required) to use one of the chip selects from groups a or b. virtually any chip select other than csa0 or csd3 would be suitable for the s1d13705 interface. in the example interface, chip select csb3 is used to control the s1d1375. a 128k byte address space is used with the s1d13705 control registers mapped into the top 32 bytes of the 128k byte block and the 80k bytes of display buffer mapped to the starting address of the block. the chip select should have its ro (read only) bit set to 0, and the wait ?ld (wait states) should be set to 111b to allow the s1d13705 to terminate bus cycles externally. 1.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. table 1-2 summary of power-on/reset options s1d13705 pin name value on this pin at the rising edge of reset# is used to con?ure: (1/0) 01 cnf0 see ?able 1-3: host bus interface selection cnf1 cnf2 cnf3 little endian big endian = con?uration for mc68328 support table 1-3 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 0 0 0 x sh-4 interface 0 0 1 x sh-3 interface 0 1 0 x reserved 0 1 1 x mc68k #1, 16-bit 1 0 0 x reserved 1 0 1 x mc68k #2, 16-bit 1100 reserved 1101 reserved 1 1 1 0 generic #1, 16-bit 1 1 1 1 generic #2, 16-bit = con?uration for mc68328 using generic #1 host bus interface = con?uration for mc68328 using mc68k #1 host bus interface 2: interfacing to the motorola mpc821 microprocessor 5-8 epson s1d13705f00a application notes (x27a-g-010-01) 2i nterfacing to the m otorola mpc821 m icroprocessor 2.1 introduction this application note describes the hardware and software environment required to interface the s1d13705 embedded memory lcd controller and the motorola mpc821 processor. 2.2 interfacing to the mpc821 the mpc8xx system bus the mpc8xx family of processors feature a high-speed synchronous system bus typical of modern risc microprocessors. this section provides an overview of the operation of the cpu bus in order to establish interface requirements. mpc821 bus overview the mpc8xx microprocessor family uses a synchronous address and data bus. all io is synchronous to a square-wave reference clock called mclk (master clock). this clock runs at the machine cycle speed of the cpu core (typically 25 to 50 mhz). most outputs from the processor change state on the rising edge of this clock. similarly, most inputs to the processor are sampled on the rising edge. note: the external bus can run at one-half the cpu core speed using the clock control register. this is typically used when the cpu core is operated above 50 mhz. the mpc821 can generate up to eight independent chip select outputs, each of which may be controlled by one of two types of timing generators: the general purpose chip select module (gpcm) or the user-programmable machine (upm). examples are given using the gpcm. it should be noted that all power pc microprocessors, including the mpc8xx family, use bit notation opposite from the convention used by most other microprocessor systems. bit numbering for the mpc8xx always starts with zero as the most signi?ant bit, and increments in value to the least- signi?ant bit. for example, the most signi?ant bits of the address bus and data bus are a0 and d0, while the least signi?ant bits are a31 and d31. the mpc8xx uses both a 32-bit address and data bus. a parity bit is supported for each of the four byte lanes on the data bus. parity checking is done when data is read from external memory or peripherals, and generated by the mpc8xx bus controller on write cycles. all io accesses are memory-mapped meaning there is no separate io space in the power pc architecture. support is provided for both on-chip (dma controllers) and off-chip (other processors and peripheral controllers) bus masters. the bus can support both normal and burst cycles. burst memory cycles are used to ?l on-chip cache memory, and for certain on-chip dma operations. normal cycles are used for all other data transfers. x27a-g-010-01 2: interfacing to the motorola mpc821 microprocessor s1d13705f00a application notes epson 5-9 (x27a-g-010-01) normal (non-burst) bus transactions a data transfer is initiated by the bus master by placing the memory address on address lines a0 through a31 and driving ts (transfer start) low for one clock cycle. several control signals are also provided with the memory address: tsiz[0:1] (transfer size) -- indicates whether the bus cycle is 8, 16, or 32-bit. rd/wr -- set high for read cycles and low for write cycles. at[0:3] (address type signals) -- provides more detail on the type of transfer being attempted. when the peripheral device being accessed has completed the bus transfer, it asserts t a (transfer acknowledge) for one clock cycle to complete the bus transaction. once t a has been asserted, the mpc821 will not start another bus cycle until t a has been de-asserted. the minimum length of a bus transaction is two bus clocks. figure 2-1 ?ower pc memory read cycle? illustrates a typical memory read cycle on the power pc system bus. figure 2-1 power pc memory read cycle a[0:31] d[0:31] tsiz[0:1], at[0:3] ts ta sysclk wait states transfer start transfer next transfer sampled when ta low rd/wr complete starts 2: interfacing to the motorola mpc821 microprocessor 5-10 epson s1d13705f00a application notes (x27a-g-010-01) figure 2-2 ?ower pc memory write cycle? illustrates a typical memory write cycle on the power pc system bus. figure 2-2 power pc memory write cycle if an error occurs, tea (transfer error acknowledge) is asserted and the bus cycle is aborted. for example, a peripheral device may assert tea if a parity error is detected, or the mpc821 bus controller may assert tea if no peripheral device responds at the addressed memory location within a bus time-out period. for 32-bit transfers, all data lines (d[0:31]) are used and the two low-order address lines a30 and a31 are ignored. for 16-bit transfers, data lines d0 through d15 are used and address line a30 is ignored. for 8-bit transfers, data lines d0 through d7 are used and all address lines (a[0:31]) are used. note: this assumes that the power pc core is operating in big endian mode (typically the case for embedded systems). burst cycles burst memory cycles are used to ?l on-chip cache memory and to carry out certain on-chip dma operations. they are very similar to normal bus cycles with the following exceptions: always 32-bit. always attempt to transfer four 32-bit words sequentially. always address longword-aligned memory (i.e. a30 and a31 are always 0:0). do not increment address bits a28 and a29 between successive transfers; the addressed device must increment these address bits internally. if a peripheral is not capable of supporting burst cycles, it can assert burst inhibit (bi ) simultaneously with t a , and the processor will revert to normal bus cycles for the remaining data transfers. burst cycles are mainly intended to facilitate cache line ?ls from program or data memory. they are normally not used for transfers to/from io peripheral devices such as the s1d13705, therefore the interfaces described in this document do not attempt to support burst cycles. however, the example interfaces include circuitry to detect the assertion of bdip and respond with bi if caching is accidently enabled for the s1d13705 address space. a[0:31] d[0:31] tsiz[0:1], at[0:3] ts ta sysclk wait states transfer start rd/wr valid transfer next transfer complete starts 2: interfacing to the motorola mpc821 microprocessor s1d13705f00a application notes epson 5-11 (x27a-g-010-01) memory controller module general-purpose chip select module (gpcm) the general-purpose chip select module (gpcm) is used to control memory and peripheral devices which do not require special timing or address multiplexing. in addition to the chip select output, it can generate active-low output enable (oe ) and write enable (we ) signals compatible with most memory and x86-style peripherals. the mpc821 bus controller also provides a read/ write (rd/wr ) signal which is compatible with most 68k peripherals. the gpcm is controlled by the values programmed into the base register (br) and option register (or) of the respective chip select. the option register sets the base address, the block size of the chip select, and controls the following timing parameters: the acs bit ?ld allows the chip select assertion to be delayed with respect to the address bus valid, by 0, 1/4, or 1/2 clock cycle. the csnt bit causes chip select and we to be negated 1/2 clock cycle earlier than normal. the trlx (relaxed timing) bit will insert an additional one clock delay between assertion of the address bus and chip select. this accommodates memory and peripherals with long setup times. the ehtr (extended hold time) bit will insert an additional 1-clock delay on the ?st access to a chip select. up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by assert- ing t a (transfer acknowledge). any chip select may be programmed to assert bi (burst inhibit) automatically when its memory space is addressed by the processor core. user-programmable machine (upm) the upm is typically used to control memory types, such as dynamic rams, which have complex control or address multiplexing requirements. the upm is a general purpose ram-based pattern generator which can control address multiplexing, wait state generation, and ?e general-purpose output lines on the mpc821. up to 64 pattern locations are available, each 32 bits wide. separate patterns may be programmed for normal accesses, burst accesses, refresh (timer) events, and exception conditions. this ?xibility allows almost any type of memory or peripheral device to be accommodated by the mpc821. in this application note, the gpcm is used instead of the upm, since the gpcm has enough ?xibility to accommodate the s1d13705 and it is desirable to leave the upm free to handle other interfacing duties, such as edo dram. 2.3 s1d13705 host bus interface this section is a summary of the host bus interface mode used on the s1d13705 to interface to the mpc821. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface mode used for the mpc821 is: generic #1 (chip select, plus individual read enable/write enable for each byte). 2: interfacing to the motorola mpc821 microprocessor 5-12 epson s1d13705f00a application notes (x27a-g-010-01) host bus interface modes for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-01. generic #1 host bus interface mode generic #1 host bus interface mode is the most general and least processor-speci? host bus interface mode on the s1d13705. the generic # 1 host bus interface mode was chosen for this interface due to the simplicity of its timing. the host bus interface requires the following signals: busclk is a clock input which is required by the s1d13705 host interface. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper io or memory address space. we0# and we1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is writing data to the s1d13705. rd# and rd/wr# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading data from the s1d13705. wait# is a signal output from the s1d13705 that indicates the host cpu must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) signal is not used in the bus interface for generic #1 mode. however, bs# is used to con?ure the s1d13705 for generic #1 mode and should be tied low (connected to gnd). table 2-1 host bus interface pin mapping s1d13705 pin names generic #1 ab[15:1] a[15:1] ab0 a0 db[15:0] d[15:0] we1# we1# cs# external decode bclk bclk bs# connect to v ss rd/wr# rd1# rd# rd0# we0# we0# wait# wait# reset# reset# 2: interfacing to the motorola mpc821 microprocessor s1d13705f00a application notes epson 5-13 (x27a-g-010-01) 2.4 mpc821 to s1d13705 interface hardware description the interface between the s1d13705 and the mpc821 requires minimal glue logic. one inverter is required to change the polarity of the wait# signal (an active low signal) to insert wait states in the bus cycle. the mpc821 transfer acknowledge signal (t a ) is an active low signal which ends the current bus cycle. the inverter is enabled using cs# so that t a is not driven by the s1d13705 during non-s1d13705 bus cycles. a single resistor is used to speed up the rise time of the wait# (t a ) signal when terminating the bus cycle. bs# (bus start) is not used in this implementation and should be tied low (connected to gnd). the following diagram shows a typical implementation of the mpc821 to s1d13705 interface. figure 2-3 typical implementation of mpc821 to s1d13705 interface mpc821 s1d13705 a[15:31] d[0:15] cs4 t a we0 we1 oe sysclk ab[16:0] db[15:0] cs# wait# we1# we0# rd/wr# rd# busclk reset# vcc 470 bs# system reset note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 2: interfacing to the motorola mpc821 microprocessor 5-14 epson s1d13705f00a application notes (x27a-g-010-01) mpc821ads evaluation board hardware connections the following table details the connections between the pins and signals of the mpc821 and the s1d13705. note: the bit numbering of the power pc bus signals is reversed from the normal convention, e.g.: the most significant address bit is a0, the next is a1, a2, etc. table 2-2 list of connections from mpc821ads to s1d13705 mpc821 signal name mpc821ads connector and pin name s1d13705 signal name vcc p6-a1, p6-b1 vcc a15 p6-d20 a16 a16 p6-b24 a15 a17 p6-c24 a14 a18 p6-d23 a13 a19 p6-d22 a12 a20 p6-d19 a11 a21 p6-a19 a10 a22 p6-d28 a9 a23 p6-a28 a8 a24 p6-c27 a7 a25 p6-a26 a6 a26 p6-c26 a5 a27 p6-a25 a4 a28 p6-d26 a3 a29 p6-b25 a2 a30 p6-b19 a1 a31 p6-d17 a0 d0 p12-a9 d15 d1 p12-c9 d14 d2 p12-d9 d13 d3 p12-a8 d12 d4 p12-b8 d11 d5 p12-d8 d10 d6 p12-b7 d9 d7 p12-c7 d8 d8 p12-a15 d7 d9 p12-c15 d6 d10 p12-d15 d5 d11 p12-a14 d4 d12 p12-b14 d3 d13 p12-d14 d2 d14 p12-b13 d1 d15 p12-c13 d0 sreset p9-d15 reset# sysclk p9-c2 busclk cs4 p6-d13 cs# ta p6-b6 to inverter enabled by cs# wait# we0 p6-b15 we1# we1 p6-a14 we0# oe p6-b16 rd/wr#, rd# gnd p12-a1, p12-b1, p12-a2, p12-b2, p12-a3, p12-b3, p12-a4, p12-b4, p12-a5, p12-b5, p12-a6, p12-b6, p12-a7 vss 2: interfacing to the motorola mpc821 microprocessor s1d13705f00a application notes epson 5-15 (x27a-g-010-01) s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02 for details. the tables below show only those con?uration settings important to the mpc821 interface. the settings are very similar to the isa bus with the following exceptions: the wait# signal is active high rather than active low. the power pc is big endian rather than little endian. table 2-3 con?uration settings signal low high cnf0 see ?ost bus interface selection?table4-3 below. see ?ost bus interface selection?table4-3 below. cnf1 cnf2 cnf3 little endian big endian = con?uration for mpc821 host bus interface table 2-4 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 1 1 1 0 generic #1, 16-bit = con?uration for mpc821 host bus interface 2: interfacing to the motorola mpc821 microprocessor 5-16 epson s1d13705f00a application notes (x27a-g-010-01) mpc821 chip select con?uration the dram on the mpc821 ads board extends from address 0 through 3f ffffh, so the s1d13705 is addressed starting at 40 0000h. the s1d13705 uses a 128k byte segment of memory starting at this address, with the ?st 80k bytes used for the display buffer and the upper 32 bytes of this memory block used for the s1d13705 internal registers. chip select 4 is used to control the s1d13705. the following options are selected in the base address register (br4): ba (0:16) = 0000 0000 0100 0000 0 - set starting address of s1d13705 to 40 0000h at (0:2) = 0 - ignore address type bits ps (0:1) = 1:0 - memory port size is 16 bits pare = 0 - disable parity checking wp = 0 - disable write protect ms (0:1) = 0:0 - select general purpose chip select module to control this chip select v = 1 - set valid bit to enable chip select the following options were selected in the option register (or4): am (0:16) = 1111 1111 1100 0000 0 - mask all but upper 10 address bits; s1d13705 consumes 4m byte of address space atm (0:2) = 0 - ignore address type bits csnt = 0 - normal cs /we negation acs (0:1) = 1:1 - delay cs assertion by 1/2 clock cycle from address lines bi = 1 - assert burst inhibit scy (0:3) = 0 - wait state selection; this ?ld is ignored since external transfer acknowledge is used; see seta below seta = 1 - the s1d13705 generates an external transfer acknowledge using the wait# line trlx = 0 - normal timing ehtr = 0 - normal timing 2: interfacing to the motorola mpc821 microprocessor s1d13705f00a application notes epson 5-17 (x27a-g-010-01) test software the test software to exercise this interface is very simple. it con?ures chip select 4 on the mpc821 to map the s1d13705 to an unused 128k byte block of address space and loads the appropriate values into the option register for cs4. at that point the software runs in a tight loop reading the s1d13705 revision code register reg[00h], which allows monitoring of the bus timing on a logic analyzer. the source code for this test routine is as follows: br4 equ $120 ; cs4 base register or4 equ $124 ; cs4 option register memstart equ $40 ; upper word of s1d13705 start address revcodereg equ 1ffe0 ; address of revision code register start mfspr r1,immr ; get base address of internal registers andis. r1,r1,$ffff ; clear lower 16 bits to 0 andis. r2,r0,0 ; clear r2 oris r2,r2,memstart ; write base address ori r2,r2,$0801 ; port size 16 bits; select gpcm; enable stw r2,br4(r1) ; write value to base register andis. r2,r0,0 ; clear r2 oris r2,r2,$ffc0 ; address mask ?use upper 10 bits ori r2,r2,$0708 ; normal cs negation; delay cs 1/2 clock; ; inhibit burst stw r2,or4(r1) ; write to option register andis. r1,r0,0 ; clear r1 oris r1,r1,memstart ; point r1 to start of s1d13705 mem space loop lbz r0,revcodereg(r1) ; read revision code into r1 b loop ; branch forever end this code was entered into the memory of the mpc821ads using the line-by-line assembler in mpc8bug, the debugger provided with the ads board. it was executed on the ads and a logic analyzer was used to verify operation of the interface hardware. note: mpc8bug does not support comments or symbolic equates; these have been added for clarity. it is important to note that when the mpc821 comes out of reset, its on-chip caches and mmu are disabled. if the data cache is enabled, then the mmu must be set up so that the s1d13705 memory block is tagged as non-cacheable, to ensure that accesses to the s1d13705 will occur in proper order, and also to ensure that the mpc821 does not attempt to cache any data read from or written to the s1d13705 or its display buffer. 2.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor 5-18 epson s1d13705f00a application notes (x27a-g-011-01) 3i nterfacing to the m otorola mcf5307 ? old f ire ?m icroprocessor 3.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the motorola mcf5307 processor. the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. 3.2 interfacing to the mcf5307 the mcf5307 system bus the mcf5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. this section is an overview of the operation of the cpu bus to establish interface requirements. overview the mcf5307 microprocessor family uses a synchronous address and data bus, very similar in architecture to the mc68040 and mpc8xx. all outputs and inputs are timed with respect to a square-wave reference clock called bclk0 (master clock). this clock runs at a software-selectable divisor rate from the machine cycle speed of the cpu core, typically 20 to 33 mhz. both the address and the data bus are 32 bits in width. all io accesses are memory-mapped; there is no separate io space in the cold?e architecture. the bus can support two types of cycles, normal and burst. burst memory cycles are used to ?l on- chip cache memories, and for certain on-chip dma operations. normal cycles are used for all other data transfers. normal (non-burst) bus transactions a data transfer is initiated by the bus master by placing the memory address on address lines a31 through a0 and driving ts (transfer start) low for one clock cycle. several control signals are also provided with the memory address: siz[1:0] (transfer size), which indicate whether the bus cycle is 8, 16, or 32 bits in width. r/w , which is high for read cycles and low for write cycles. a set of transfer type signals (tt[1:0]) which provide more detail on the type of transfer being attempted. tip (transfer in progress), which is asserted whenever a bus cycle is active. when the peripheral device being accessed has completed the bus transfer, it asserts t a (transfer acknowledge) for one clock cycle, completing the bus transaction. once t a has been asserted, the mcf5307 will not start another bus cycle until t a has been de-asserted. the minimum length of a bus transaction is two bus clocks. x27a-g-011-01 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor s1d13705f00a application notes epson 5-19 (x27a-g-011-01) figure 3-1 illustrates a typical memory read cycle on the mcf5307 system bus, and figure 3-2 illustrates a memory write cycle. figure 3-1 mcf5307 memory read cycle figure 3-2 mcf5307 memory write cycle a[31:0] d[31:0] siz[1:0], tt[1:0] ts ta bclk0 wait states transfer start transfer next transfer sampled when ta low r/w complete starts tip a[31:0] d[31:0] siz[1:0], tt[1:0] ts ta bclk0 wait states transfer start r/w valid transfer next transfer complete starts tip 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor 5-20 epson s1d13705f00a application notes (x27a-g-011-01) burst cycles burst cycles are very similar to normal cycles, except that they occur as a series of four back-to- back, 32-bit memory reads or writes, with the tip (transfer in progress) output asserted continuously through the burst. burst memory cycles are mainly intended to facilitate cache line ?l from program or data memory; they are typically not used for transfers to or from io peripheral devices such as the s1d13705. the mcf5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them. chip-select module in addition to generating eight independent chip-select outputs, the mcf5307 chip select module can generate active-low output enable (oe ) and write enable (bwe ) signals compatible with most memory and x86-style peripherals. the mcf5307 bus controller also provides a read/write (r/w ) signal which is compatible with most 68k peripherals. chip selects 0 and 1 can be programmed independently to respond to any base address and block size. chip select 0 can be active immediately after reset, and is typically used to control a boot rom. chip select 1 is likewise typically used to control a large static or dynamic ram block. chip selects 2 through 7 have ?ed block sizes of 2m bytes each. each has a unique, ?ed offset from a common, programmable starting address. these chip selects are well-suited to typical io addressing requirements. each chip select may be individually programmed for port size (8/16/32 bits), 0 to 15 wait states or external acknowledge, address space type, burst or non-burst cycle support, and write protect. 3.3 s1d13705 bus interface this section is a summary of the host bus interface mode used on the s1d13705 to interface to the mcf5307. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface mode used for the mcf5307 is: generic #1 (chip select, plus individual read enable/write enable for each byte). host bus pin connection for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. table 3-1 host bus interface pin mapping s1d13705 pin names generic #1 ab[15:1] a[15:1] ab0 a0 db[15:0] d[15:0] we1# we1# cs# external decode bclk bclk bs# connect to v ss rd/wr# rd1# rd# rd0# we0# we0# wait# wait# reset# reset# 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor s1d13705f00a application notes epson 5-21 (x27a-g-011-01) generic #1 interface mode generic #1 interface mode is the most general and least processor-speci? interface mode on the s1d13705. the generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. the interface requires the following signals: busclk is a clock input which is required by the s1d13705 host interface. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we0# and we1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is writing data to the s1d13705. rd# and rd/wr# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading data from the s1d13705. wait# is a signal output from the s1d13705 that indicates the host cpu must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) signal is not used in the bus interface for generic #1 mode. however, bs# is used to con?ure the s1d13705 for generic #1 mode and should be tied low (connected to gnd). 3.4 mcf5307 to s1d13705 interface hardware description the s1d13705 is interfaced to the mcf5307 with a minimal amount of glue logic. one inverter is required to change the polarity of the wait# signal, which is an active low signal to insert wait states in the bus cycle, while the mcf5307 s transfer acknowledge signal (t a ) is an active low signal to end the current bus cycle. the inverter is enabled by cs# so that t a is not driven by the s1d13705 during non-s1d13705 bus cycles. a single resistor is used to speed up the rise time of the wait# (t a ) signal when terminating the bus cycle. 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor 5-22 epson s1d13705f00a application notes (x27a-g-011-01) the following diagram shows a typical implementation of the mcf5307 to s1d13705 interface. figure 3-3 typical implementation of mcf5307 to s1d13705 interface s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. table 3-2, ?ummary of power-on/reset options,?on page 5-22 and table 3-3, ?ost bus interface selection,?on page 5-22 shows the settings used for the s1d13705 in this interface. table 3-2 summary of power-on/reset options s1d13705 pin name value on this pin at the rising edge of reset# is used to con?ure: (0/1) 01 cnf0 see ?ost bus interface selection?table3-3 below. see ?ost bus interface selection?table3-3 below. cnf1 cnf2 cnf3 little endian big endian = con?uration for mfc5307 support table 3-3 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 1 1 1 0 generic #1, 16-bit = con?uration for mfc5307 support mcf5307 s1d13705 a[16:0] d[31:16] cs4 t a bwe1 bwe0 oe bclk0 ab[16:0] db[15:0] cs# wait# we1# we0# rd/wr# rd# busclk reset# vcc 470 bs# system reset note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 3: interfacing to the motorola mcf5307 ?oldfire?microprocessor s1d13705f00a application notes epson 5-23 (x27a-g-011-01) mcf5307 chip select con?uration chip selects 0 and 1 have programmable block sizes from 64k bytes through 2g bytes. however, these chip selects would normally be needed to control system ram and rom. therefore, one of the io chip selects cs2 through cs7 is required to address the entire address space of the s1d13705. these io chip selects have a ?ed, 2m byte block size. in the example interface, chip select 4 is used to control the s1d13705. the s1d13705 only uses a 128k byte block with its 80k byte display buffer residing at the start of this 128k byte block and its internal registers occupying the last 32 bytes of this block. this block of memory will be shadowed over the entire 2m byte space. the csbar register should be set to the upper 8 bits of the desired base address. the following options should be selected in the chip select mask registers (csmr4/5): wp = 0 - disable write protect am = 0 - enable alternate bus master access to the s1d13705 c/i = 1 - disable cpu space access to the s1d13705 sc = 1 - disable supervisor code space access to the s1d13705 sd = 0 - enable supervisor data space access to the s1d13705 uc = 1 - disable user code space access to the s1d13705 ud = 0 - enable user data space access to the s1d13705 v = 1 - global enable (?alid? for the chip select the following options should be selected in the chip select control registers (cscr4/5): ws0-3 = 0 - no internal wait state setting aa = 0 - no automatic acknowledgment ps (1:0) = 1:0 - memory port size is 16 bits bem = 0 - byte enable/write enable active on writes only bstr = 0 - disable burst reads bstw = 0 - disable burst writes 3.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. 4: interfacing to the pc card bus 5-24 epson s1d13705f00a application notes (x27a-g-009-01) 4i nterfacing to the pc c ard b us 4.1 introduction this application note describes the hardware and software environment required to interface the s1d13705 embedded memory lcd controller and the pc card (pcmcia) bus. 4.2 interfacing to the pc card bus the pc card system bus pc card technology has gained wide acceptance in the mobile computing ?ld as well as in other markets due to its portability and ruggedness. this section is an overview of the operation of the 16- bit pc card interface conforming to the pcmcia 2.0/jeida 4.1 standard (or later). pc card overview the 16-bit pc card provides a 26-bit address bus and additional control lines which allow access to three 64m byte address ranges. these ranges are used for common memory space, io space, and attribute memory space. common memory may be accessed by a host system for memory read and write operations. attribute memory is used for de?ing card speci? information such as con?uration registers, card capabilities, and card use. io space maintains software and hardware compatibility with hosts such as the intel x86 architecture, which address peripherals independently from memory space. bit notation follows the convention used by most microprocessors, the high bit is the most signi?ant. therefore, signals a25 and d15 are the most signi?ant bits for the address and data bus respectively. support is provided for on-chip dma controllers. pc card bus signals are asynchronous to the host cpu bus signals. bus cycles are started with the assertion of either the ce1# and/or the ce2# card enable signals. the cycle ends once these signals are de-asserted. bus cycles can be lengthened using the wait# signal. note: the pcmcia 2.0/jeida 4.1 (and later) pc card standard support the two signals wait# and re- set which are not supported in earlier versions of the standard. the wait# signal allows for asyn- chronous data transfers for memory, attribute, and io access cycles. the reset signal allows resetting of the card configuration by the reset line of the host cpu. x27a-g-009-01 4: interfacing to the pc card bus s1d13705f00a application notes epson 5-25 (x27a-g-009-01) memory access cycles a data transfer is initiated when the memory address is placed on the pc card bus and one, or both, of the card enable signals (ce1# and ce2#) are driven low. reg# must be kept inactive. if only ce1# is driven low, 8-bit data transfers are enabled and a0 speci?s whether the even or odd data byte appears on data bus lines d[7:0]. if both ce1# and ce2# are driven low, a 16-bit word transfer takes place. if only ce2# is driven low, an odd byte transfer occurs on data lines d[15:8]. during a read cycle, oe# (output enable) is driven low. a write cycle is speci?d by driving oe# high and driving the write enable signal (we#) low. the cycle can be lengthened by driving wait# low for the time needed to complete the cycle. figure 4-1 and figure 4-2 illustrate typical memory access cycles on the pc card bus. figure 4-1 pc card read cycle figure 4-2 pc card write cycle a[25:0] ce1# oe# wait# address valid data valid hi-z hi-z d[15:0] reg# ce2# transfer start transfer complete a[25:0] ce1# oe# wait# address valid data valid hi-z hi-z d[15:0] reg# ce2# transfer start transfer complete we# 4: interfacing to the pc card bus 5-26 epson s1d13705f00a application notes (x27a-g-009-01) 4.3 s1d13705 bus interface this section is a summary of the host bus interface modes available on the s1d13705 that would be used to interface to the pc card bus. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface mode used for the pc card bus is: generic #2 (external chip select, shared read/write enable for high byte, individual read/write enable for low byte). host bus pin connection the following table shows the functions of the host bus interface signals. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. generic #2 interface mode generic #2 interface mode is a general and non-processor-speci? interface mode on the s1d13705. the generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the pc card bus control signals. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we1# is the high byte enable for both read and write cycles. we0# is the write enable for the s1d13705, to be driven low when the host cpu is writing data to the s1d13705. rd# is the read enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. table 4-1 host bus interface pin mapping s1d13705 pin names generic #2 ab[15:1] a[15:1] ab0 a0 db[15:0] d[15:0] we1# bhe# cs# external decode bclk bclk bs# connect to io v dd rd/wr# connect to io v dd rd# rd# we0# we# wait# wait# reset# reset# 4: interfacing to the pc card bus s1d13705f00a application notes epson 5-27 (x27a-g-009-01) wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) and read/write (rd/wr#) signals are not used in the bus interface for generic #2 mode. however, bs# is used to con?ure the s1d13705 for generic #2 mode and should be tied high (connected to io v dd ). rd/wr# should also be tied high. 4.4 pc card to s1d13705 interface hardware connections the s1d13705 is interfaced to the pc card bus with a minimal amount of glue logic. in this implementation, the address inputs (ab[16:0]) and data bus (db[15:0] connect directly to the cpu address (a[16:0]) and data bus (d[15:0]). the pc card interface does not provide a bus clock, so one must be supplied for the s1d13705. since the bus clock frequency is not critical, nor does it have to be synchronous to the bus signals, it may be the same as clki. bs# (bus start) is not used by generic #2 mode but is used to con?ure the s1d13705 for either generic #1 or generic #2 bus and should be tied high (connected to io v dd ). rd/wr# is also not used by generic #2 bus and should be tied high (connected to io v dd ). the following diagram shows a typical implementation of the pc card to s1d13705 interface. figure 4-3 typical implementation of pc card to s1d13705 interface rd/wr# rd# db[15:0] wait# busclk s1d13705 reset# ab[16:0] oe# d[15:0] wait# a[16:0] pc card socket 15k pull-up clki oscillator we1# we0# cs# we# ce1# ce2# reset io v dd bs# io v dd note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 4: interfacing to the pc card bus 5-28 epson s1d13705f00a application notes (x27a-g-009-01) s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02 for details. the tables below show only those con?uration settings important to the pc card host bus interface. register/memory mapping the s1d13705 is a memory mapped device. the s1d13705 memory may be addressed starting at 0000h, or on consecutive 128k byte blocks, and its internal registers are located in the upper 32 bytes of the 128k byte block (i.e. reg[0] = 1ffe0h). while the pc card socket provides 64m bytes of memory address space, the s1d13705 only needs a 128k byte block of memory to accommodate its 80k byte display buffer and its 32 byte register set. for this reason only address bits a[16:0] are used while a[25:17] are ignored. because the entire 64m bytes of memory is available, the s1d13705 s memory and registers will be aliased every 128k bytes for a total of 512 times. note: if aliasing is not desirable, the upper addresses must be fully decoded. 4.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. table 4-2 summary of power-on/reset options signal low high cnf0 see ?ost bus interface selection?table4-3 below. see ?ost bus interface selection?table4-3 below. cnf1 cnf2 cnf3 little endian big endian = con?uration for pc card host bus interface table 4-3 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 1 1 1 1 generic #2, 16-bit = con?uration for pc card host bus interface 5: interfacing to the toshiba mips tmpr3912 microprocessor s1d13705f00a application notes epson 5-29 (x27a-g-004-01) 5i nterfacing to the t oshiba mips tmpr3912 m icroprocessor 5.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the toshiba mips tmpr3912 processor. the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. 5.2 interfacing to the tmpr3912 the toshiba mips tmpr3912 processor supports up to two pc card (pcmcia) slots. it is through this host bus interface that the s1d13705 connects to the tmpr3912 processor. the s1d13705 can be successfully interfaced using one of two con?urations: direct connection to tmpr3912. system design using one ite it8368e pc card/gpio buffer chip. 5.3 s1d13705 host bus interface this section is a summary of the host bus interface modes available on the s1d13705 that would be used to interface to the tmpr3912. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface modes used for the tmpr3912 are: generic #1 (chip select, plus individual read enable/write enable for each byte). generic #2 (external chip select, shared read/write enable for high byte, individual read/write enable for low byte). host bus pin connection the following table shows the functions of each host bus interface signal. for con?uration details, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. x27a-g-004-01 table 5-1 host bus interface pin mapping s1d13705 pin names generic #1 generic #2 ab[15:1] a[15:1] a[15:1] ab0 a0 a0 db[15:0] d[15:0] d[15:0] we1# we1# bhe# cs# external decode external decode bclk bclk bclk bs# connect to v ss connect to io v dd rd/wr# rd1# connect to io v dd rd# rd0# rd# we0# we0# we# wait# wait# wait# reset# reset# reset# 5: interfacing to the toshiba mips tmpr3912 microprocessor 5-30 epson s1d13705f00a application notes (x27a-g-004-01) generic #1 interface mode generic #1 interface mode is the most general and least processor-speci? interface mode on the s1d13705. the generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. the interface requires the following signals: busclk is a clock input which is required by the s1d13705 host interface. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we0# and we1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is writing data to the s1d13705. these signals must be generated by external hardware based on the control outputs from the host cpu. rd# and rd/wr# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading data from the s1d13705. these signals must be gener- ated by external hardware based on the control outputs from the host cpu. wait# is a signal output from the s1d13705 that indicates the host cpu must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) signal is not used in the bus interface for generic #1 mode. however, bs# is used to con?ure the s1d13705 for generic #1 mode and should be tied low (connected to gnd). 5: interfacing to the toshiba mips tmpr3912 microprocessor s1d13705f00a application notes epson 5-31 (x27a-g-004-01) generic #2 interface mode generic #2 interface mode is a general and non-processor-speci? interface mode on the s1d13705. the generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the tmpr3912 control signals. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we1# is the high byte enable for both read and write cycles for the s1d13705, to be driven low when the host cpu accesses the s1d13705. we0# is the write enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. rd# is the read enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the 13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) and read/write (rd/wr#) signals are not used in the bus interface for generic #2 mode. however, bs# is used to con?ure the s1d13705 for generic #2 mode and should be tied high (connected to io v dd ). rd/wr# should also be tied high. 5.4 direct connection to the toshiba tmpr3912 general description in this example implementation, the s1d13705 occupies the tmpr3912 pc card slot #1. the s1d13705 is easily interfaced to the tmpr3912 with minimal additional logic. the address bus of the tmpr3912 pc card interface is multiplexed and must be demultiplexed using an advanced cmos latch (e.g., 74ahc373). the direct connection approach makes use of the s1d13705 in its ?eneric interface #2?con?uration. the following diagram demonstrates a typical implementation of the interface. 5: interfacing to the toshiba mips tmpr3912 microprocessor 5-32 epson s1d13705f00a application notes (x27a-g-004-01) figure 5-1 s1d13705 to tmpr3912 direct connection note: see section , ?ost bus pin connection?on page 5-29 and section , ?eneric #2 interface mode?on page 5-26 for generic #2 pin descriptions. the ?eneric #2?host interface control signals of the s1d13705 are asynchronous with respect to the s1d13705 bus clock. this gives the system designer full ?xibility to choose the appropriate source (or sources) for clki and bclk. the choice of whether both clocks should be the same, and whether to use dclkout (divided) as clock source, should be based on the desired: pixel and frame rates. power budget. part count. maximum s1d13705 clock frequencies. the s1d13705 also has internal clock dividers providing additional ?xibility. memory mapping and aliasing in this example implementation the tmpr3912 control signal cardreg* is ignored; therefore the s1d13705 takes up the entire pc card slot 1. the s1d13705 requires an addressing space of 128k bytes. the on-chip display memory occupies the range 0 through 13fffh. the registers occupy the range 1ffe0h through 1ffffh. the tmpr3912 demultiplexed address lines a17 and above are ignored, thus the s1d13705 is aliased 512 times at 128k byte intervals over the 64m byte pc card slot #1 memory space. note: if aliasing is undesirable, additional decoding circuitry must be added. we0# rd# db[7:0] wait# bclk s1d13705 reset# ab[16:13] d[31:24] card1wait* a[12:0] tmpr3912 pull-up oscillator we1# card1csl* card1csh* latch ale system reset cardiowr* cardiord* bs# rd/wr# +3.3v +3.3v endian db[15:8] d[23:16] ab[12:0] v dd dclkout ...or... cs# clki see text clock divider io v dd , core v dd +3.3v note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 5: interfacing to the toshiba mips tmpr3912 microprocessor s1d13705f00a application notes epson 5-33 (x27a-g-004-01) s1d13705 con?uration the s1d13705 is con?ured at power up by latching the state of the cnf[3:0] pins. pin bs# also plays a role in host bus interface con?uration. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. the table below shows those con?uration settings relevant to the direct connection approach. 5.5 using the ite it8368e pc card buffer if the system designer uses the ite it8368e pc card and multiple-function i/o buffer, the s1d13705 can be interfaced so that it ?hares?a pc card slot. the s1d13705 is mapped to a rarely- used 16m byte portion of the pc card slot buffered by the it8368e, making the s1d13705 virtually transparent to pc card devices that use the same slot. hardware description the ite8368e has been specially designed to support epson lcd controllers and provides eleven multi-function io pins (mfio). con?uration registers may be used to allow these mfio pins to provide the control signals required to implement the s1d13705 cpu interface. the tmpr3912 processor only provides addresses a[12:0], therefore devices requiring more address space must use an external device to latch a[25:13]. the it8368e s mfio pins can be con?ured to provide this latched address. table 5-2 s1d13705 con?uration for direct connection s1d13705 con?uration pin value hard wired on this pin is used to con?ure: 1 (io v dd ) 0 (v ss ) bs# generic #2 generic #1 cnf3 big endian little endian cnf[2:0] 111: generic #1 or #2 = con?uration for toshiba tmpr3912 host bus interface 5: interfacing to the toshiba mips tmpr3912 microprocessor 5-34 epson s1d13705f00a application notes (x27a-g-004-01) figure 5-2 s1d13705 to tmpr3912 connection using an it8368e note: see section , ?ost bus pin connection?on page 5-29 and section , ?eneric #1 interface mode?on page 5-30 for generic #1 pin descriptions. the ?eneric #1?host interface control signals of the s1d13705 are asynchronous with respect to the s1d13705 bus clock. this gives the system designer full ?xibility to choose the appropriate source (or sources) for clki and bclk. the choice of whether both clocks should be the same, and whether to use dclkout (divided) as clock source, should be based on pixel and frame rates, power budget, part count and maximum s1d13705 respective clock frequencies. also, internal s1d13705 clock dividers provide additional ?xibility. it8368e con?uration the it8368e provides eleven multi-function io pins (mfio). the it8368e must have both ?ix attribute/io?and ?ga?modes on. when both these modes are enabled, the mfio pins provide control signals needed by the s1d13705 host bus interface, and a 16m byte portion of the system pc card attribute and io space is allocated to address the s1d13705. when accessing the s1d13705 the associated card-side signals are disabled in order to avoid any con?cts. for mapping details, refer to section 3.3: ?emory mapping and aliasing. for connection details see figure 5-2, ?1d13705 to tmpr3912 connection using an it8368e,?above. for further information on the it8368e, refer to the ?t8368e pc card/gpio buffer chip speci?ation? note: when a second it8368e is used, that circuit should not be set in vga mode. it8368e s1d13705 a[12:0] ab[12:0] d[31:24] db[7:0] lha[23]/mfio[10] we1# we0# rd/wr# rd# cs# lha[22]/mfio[9] lha[21]/mfio[8] lha[20]/mfio[7] lha[19]/mfio[6] wait# cardxwait* reset# ab[16:13] tmpr3912 d[23:16] db[16:8] dclkout endian system reset lha[16:13]/ oscillator ...or... pull-up v dd bclk clki see text clock divider bs# io v dd , core v dd +3.3v mfio[3:0] note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 5: interfacing to the toshiba mips tmpr3912 microprocessor s1d13705f00a application notes epson 5-35 (x27a-g-004-01) memory mapping and aliasing when the tmpr3912 accesses the pc card slots without the ite it8368e, its system memory is mapped as in table 5-3 . note: bit card1ioen or card2ioen, depending on which card slot is used, must to be set to 0 in the tmpr3912 memory configuration register 3. when the tmpr3912 accesses the pc card slots buffered through the ite it8368e, bits card1ioen and card2ioen are ignored and the attribute/io space of the tmpr3912 is divided into attribute, i/o and s1d13705 access. details of the attribute/io address reallocation by the it8368e are found in table 5-3 . s1d13705 con?uration the s1d13705 is con?ured at power up by latching the state of the cnf[3:0] pins. pin bs# also plays a role in host bus interface con?uration. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x26a-a-001-02. the table below shows those con?uration settings relevant to this speci? interface. 5.6 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. table 5-3 tmpr3912 to pc card slots address mapping with and without the it8368e pc card slot # tmpr3912 address size using the ite it8368e direct connection, cardnioen=0 direct connection, cardnioen=1 1 0800 0000h 16m byte card 1 io s1d13705 (aliased 512 times at 128k byte intervals) card 1 io 0900 0000h 16m byte s1d13705 (aliased 128 times at 128k byte intervals) 0a00 0000h 32m byte card 1 attribute 6400 0000h 64m byte card 1 memory s1d13705 (aliased 512 times at 128k byte intervals) 2 0c00 0000h 16m byte card 2 io s1d13705 (aliased 512 times at 128k byte intervals) card 2 io 0d00 0000h 16m byte s1d13705 (aliased 128 times at 128k byte intervals) 0e00 0000h 32m byte card 2 attribute 6800 0000h 64m byte card 2 memory s1d13705 (aliased 512 times at 128k byte intervals) table 5-4 s1d13705 con?uration using the it8368e s1d13705 con?uration pin value hard wired on this pin is used to con?ure: 1 (io v dd ) 0 (v ss ) bs# generic #2 generic #1 cnf3 big endian little endian cnf[2:0] 111: generic #1 or #2 = con?uration for connection using ite it8368e 6: interfacing to the philips mips pr31500/pr31700 processor 5-36 epson s1d13705f00a application notes (x27a-g-012-01) 6i nterfacing to the p hilips mips pr31500/pr31700 p rocessor 6.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the philips mips pr31500/pr31700 processor. the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. 6.2 interfacing to the pr31500/pr31700 the philips mips pr31500/pr31700 processor supports up to two pc card (pcmcia) slots. it is through this host bus interface that the s1d13705 connects to the pr31500/pr31700 processor. the s1d13705 can be successfully interfaced using one of two con?urations: direct connection to pr31500/pr31700 (see section 5.4, ?irect connection to the toshiba tmpr3912? on page 5-31). system design using one ite it8368e pc card/gpio buffer chip (see section 5.5, ?sing the ite it8368e pc card buffer? on page 5-33). 6.3 s1d13705 host bus interface this section is a summary of the host bus interface modes available on the s1d13705 that would be used to interface to the pr31500/pr31700. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface modes used for the pr31500/pr31700 are: generic #1 (chip select, plus individual read enable/write enable for each byte). generic #2 (external chip select, shared read/write enable for high byte, individual read/write enable for low byte). x27a-g-012-01 6: interfacing to the philips mips pr31500/pr31700 processor s1d13705f00a application notes epson 5-37 (x27a-g-012-01) host bus pin connection the following table shows the functions of each host bus interface signal. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. generic #1 interface mode generic #1 interface mode is the most general and least processor-speci? interface mode on the s1d13705. the generic # 1 interface mode was chosen for this interface due to the simplicity of its timing. the interface requires the following signals: busclk is a clock input which is required by the s1d13705 host interface. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we0# and we1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is writing data to the s1d13705. these signals must be generated by external hardware based on the control outputs from the host cpu. rd# and rd/wr# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host cpu is reading data from the s1d13705. these signals must be gener- ated by external hardware based on the control outputs from the host cpu. wait# is a signal output from the s1d13705 that indicates the host cpu must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) signal is not used in the bus interface for generic #1 mode. however, bs# is used to con?ure the s1d13705 for generic #1 mode and should be tied low (connected to gnd). table 6-1 host bus interface pin mapping s1d13705 pin names generic #1 generic #2 ab[15:1] a[15:1] a[15:1] ab0 a0 a0 db[15:0] d[15:0] d[15:0] we1# we1# bhe# cs# external decode external decode bclk bclk bclk bs# connect to v ss connect to io v dd rd/wr# rd1# connect to io v dd rd# rd0# rd# we0# we0# we# wait# wait# wait# reset# reset# reset# 6: interfacing to the philips mips pr31500/pr31700 processor 5-38 epson s1d13705f00a application notes (x27a-g-012-01) generic #2 interface mode generic #2 interface mode is a general and non-processor-speci? interface mode on the s1d13705. the generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the pr31500/pr31700 control signals. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we1# is the high byte enable for both read and write cycles. we0# is the write enable signal for the s1d13705, to be driven low when the host cpu is writing data from the s1d13705. rd# is the read enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the 13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) and read/write (rd/wr#) signals are not used in the bus interface for generic #2 mode. however, bs# is used to con?ure the s1d13705 for generic #2 mode and should be tied high (connected to io v dd ). rd/wr# should also be tied high. 6: interfacing to the philips mips pr31500/pr31700 processor s1d13705f00a application notes epson 5-39 (x27a-g-012-01) 6.4 direct connection to the philips pr31500/pr31700 general description in this example implementation the s1d13705 occupies the pr31500/pr31700 pc card slot #1. the s1d13705 is easily interfaced to the pr31500/pr31700 with minimal additional logic. the address bus of the pr31500/pr31700 pc card interface is multiplexed and must be demultiplexed using an advanced cmos latch (e.g., 74ahc373). the direct connection approach makes use of the s1d13705 in its ?eneric #2?interface con?uration. the following diagram demonstrates a typical implementation of the interface. figure 6-1 s1d13705 to pr31500/pr31700 direct connection note: see section , ?ost bus pin connection?on page 5-29 and section , ?eneric #2 interface mode?on page 5-26 for generic #2 pin descriptions. the ?eneric #2?host interface control signals of the s1d13705 are asynchronous with respect to the s1d13705 bus clock. this gives the system designer full ?xibility to choose the appropriate source (or sources) for clki and bclk. the choice of whether both clocks should be the same, and whether to use dclkout (divided) as clock source, should be based on the desired: pixel and frame rates. power budget. part count. maximum s1d13705 clock frequencies. the s1d13705 also has internal clock dividers providing additional ?xibility. we0# rd# db[7:0] wait# bclk s1d13705 reset# ab[16:13] d[31:24] /card1wait a[12:0] pr31500/pr31700 pull-up oscillator we1# /card1csl /card1csh latch ale system reset /cardiowr /cardioread bs# rd/wr# +3.3v +3.3v endian db[15:8] d[23:16] ab[12:0] v dd dclkout ...or... cs# clki see text clock divider io v dd , core v dd +3.3v note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 6: interfacing to the philips mips pr31500/pr31700 processor 5-40 epson s1d13705f00a application notes (x27a-g-012-01) memory mapping and aliasing the s1d13705 requires an addressing space of 128k bytes. the on-chip display memory occupies the range 0 through 13fffh. the registers occupy the range 1ffe0h through 1ffffh. the pr31500/pr31700 demultiplexed address lines a17 and above are ignored, thus the s1d13705 is aliased 512 times at 128k byte intervals over the 64m byte pc card slot #1 memory space. in this example implementation, the pr31500/pr31700 control signal /cardreg is ignored; therefore the s1d13705 also takes up the entire pc card slot 1 con?uration space. note: if aliasing is undesirable, additional decoding circuitry must be added. s1d13705 con?uration and pin mapping the s1d13705 is con?ured at power up by latching the state of the cnf[3:0] pins. pin bs# also plays a role in host bus interface con?uration. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. the table below shows those con?uration settings relevant to the direct connection approach. 6.5 using the ite it8368e pc card buffer if the system designer uses the ite it8368e pc card and multiple-function i/o buffer, the s1d13705 can be interfaced so that it ?hares?a pc card slot. the s1d13705 is mapped to a rarely- used 16m byte portion of the pc card slot buffered by the it8368e. this makes the s1d13705 virtually transparent to pc card devices that use the same slot. hardware description the ite8368e has been specially designed to support epson lcd controllers. the ite it8368e provides eleven multi-function io pins (mfio). con?uration registers may be used to allow these mfio pins to provide the control signals required to implement the s1d13705 cpu interface. the pr31500/pr31700 processor only provides addresses a[12:0]; therefore devices requiring more address space must use an external device to latch a[25:13]. the it8368e s mfio pins can be con?ured to provide this latched address. table 6-2 s1d13705 con?uration for direct connection s1d13705 con?uration pin value hard wired on this pin is used to con?ure: 1 (io v dd ) 0 (v ss ) bs# generic #2 generic #1 cnf3 big endian little endian cnf[2:0] 111: generic #1 or #2 = con?uration for philips pr31500/pr31700 host bus interface 6: interfacing to the philips mips pr31500/pr31700 processor s1d13705f00a application notes epson 5-41 (x27a-g-012-01) figure 6-2 s1d13705 to pr31500/pr31700 connection using an it8368e note: see section on page 29 and section on page 30 for generic #1 pin descriptions. the ?eneric #1?host interface control signals of the s1d13705 are asynchronous with respect to the s1d13705 bus clock. this gives the system designer full ?xibility to choose the appropriate source (or sources) for clki and bclk. the choice of whether both clocks should be the same, and whether to use dclkout (divided) as clock source, should be based on the desired: pixel and frame rates. power budget. part count. maximum s1d13705 clock frequencies. the s1d13705 also has internal clock dividers providing additional ?xibility. it8368e s1d13705 ha[12:0] ab[12:0] hd[31:24] db[7:0] lha[23]/mfio[10] we1# we0# rd/wr# rd# cs# lha[22]/mfio[9] lha[21]/mfio[8] lha[20]/mfio[7] lha[19]/mfio[6] wait# /cardxwait reset# ab[16:13] pr31500/pr31700 hd[23:16] db[15:8] dclkout endian system reset lha[16:13]/ oscillator ...or... pull-up v dd bclk clki see text clock divider bs# io v dd , core v dd +3.3v mfio[3:0] note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 6: interfacing to the philips mips pr31500/pr31700 processor 5-42 epson s1d13705f00a application notes (x27a-g-012-01) it8368e con?uration the it8368e provides eleven multi-function io pins (mfio). the it8368e must have both ?ix attribute/io?and ?ga?modes on. when both these modes are enabled, the mfio pins provide control signals needed by the s1d13705 host bus interface, and a 16m byte portion of the system pc card attribute and io space is allocated to address the s1d13705. when accessing the s1d13705 the associated card-side signals are disabled in order to avoid any con?cts. for mapping details, refer to section 3.3: ?emory mapping and aliasing. for connection details see figure 5-2, ?1d13705 to tmpr3912 connection using an it8368e, on page 5-34. for further information on the it8368e, refer to the ?t8368e pc card/gpio buffer chip speci?ation . note: when a second it8368e is used, that circuit should not be set in vga mode. memory mapping and aliasing when the pr31500/pr31700 accesses the pc card slots without the ite it8368e, its system memory is mapped as in table 6-3 . note: bit card1ioen or card2ioen, depending on which card slot is used, must to be set to 0 in the pr31500/pr31700 memory configuration register 3. when the pr31500/pr31700 accesses the pc card slots buffered through the ite it8368e, bits card1ioen and card2ioen are ignored and the attribute/io space of the pr31500/pr31700 is divided into attribute, i/o and s1d13705 access. table 6-3 provides all details of the attribute/io address reallocation by the it8368e. s1d13705 con?uration the s1d13705 is con?ured at power up by latching the state of the cnf[3:0] pins. pin bs# also plays a role in host bus interface con?uration. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. the table below shows those con?uration settings relevant to this speci? interface. table 6-3 pr31500/pr31700 to pc card slots address mapping with and without the it8368e pc card slot # tx3912 address size using the ite it8368e direct connection, cardnioen=0 direct connection, cardnioen=1 1 0800 0000h 16m byte card 1 io s1d13705 (aliased 512 times at 128k byte intervals) card 1 io 0900 0000h 16m byte s1d13705 (aliased 128 times at 128k byte intervals) 0a00 0000h 32m byte card 1 attribute 6400 0000h 64m byte card 1 memory s1d13705 (aliased 512 times at 128k byte intervals) 2 0c00 0000h 16m byte card 2 io s1d13705 (aliased 512 times at 128k byte intervals) card 2 io 0d00 0000h 16m byte s1d13705 (aliased 128 times at 128k byte intervals) 0e00 0000h 32m byte card 2 attribute 6800 0000h 64m byte card 2 memory s1d13705 (aliased 512 times at 128k byte intervals) table 6-4 s1d13705 con?uration using the it8368e s1d13705 con?uration pin value hard wired on this pin is used to con?ure: 1 (io v dd ) 0 (v ss ) bs# generic #2 generic #1 cnf3 big endian little endian cnf[2:0] 111: generic #1 or #2 = con?uration for connection using ite it8368e 6: interfacing to the philips mips pr31500/pr31700 processor s1d13705f00a application notes epson 5-43 (x27a-g-012-01) 6.6 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. 7: interfacing to the nec vr4102/vr4111 microprocessor 5-44 epson s1d13705f00a application notes (x27a-g-008-01) 7i nterfacing to the nec vr4102/ vr4111 m icroprocessor 7.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the nec vr4102/vr4111 microprocessor ( pd30102). the nec vr4102/vr4111 microprocessor is speci?ally designed to support an external lcd controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. 7.2 interfacing to the nec vr4102/vr4111 the nec vr4102/vr4111 system bus the vr-series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. designed with external lcd controller support and windows ce-based embedded consumer applications in mind, the vr4102/vr4111 offers a highly integrated solution for portable systems. this section is an overview of the operation of the cpu bus to establish interface requirements. overview the nec vr4102/vr4111 is designed around the risc architecture developed by mips. this microprocessor is designed around the 66mhz vr4100 cpu core which supports 64-bit processing. the cpu communicates with the bus control unit (bcu) with its internal sysad bus. the bcu in turn communicates with external devices with its add and dat buses that can be dynamically sized to 16 or 32-bit operation. the nec vr4102/vr4111 has direct support for an external lcd controller. speci? control signals are assigned for an external lcd controller that provide an easy interface to the cpu. a 16m byte block of memory is assigned for the lcd controller with its own chip select and ready signals available. word or byte accesses are controlled by the system high byte signal, shb#. x27a-g-008-01 7: interfacing to the nec vr4102/vr4111 microprocessor s1d13705f00a application notes epson 5-45 (x27a-g-008-01) lcd memory access cycles once an address in the lcd block of memory is placed on the external address bus, add[25:0], the lcd chip select, lcdcs#, is driven low. the read or write enable signals, rd# and wr#, are driven low for the appropriate cycle. lcdrdy is driven low by the s1d13705 to insert wait states into the cycle. the high byte enable is driven low for 16-bit transfers and high for 8-bit transfers. figure 7-1, ?ec vr4102/vr4111 read/write cycles,?below, shows the read and write cycles to the lcd controller interface. figure 7-1 nec vr4102/vr4111 read/write cycles tclk add[25:0] lcdcs# wr#,rd# lcdrdy valid valid valid hi-z hi-z d[15:0] d[15:0] (write) (read) shb# 7: interfacing to the nec vr4102/vr4111 microprocessor 5-46 epson s1d13705f00a application notes (x27a-g-008-01) 7.3 s1d13705 host bus interface this section is a summary of the host bus interface modes available on the s1d13705 that would be used to interface to the vr4102/vr4111. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface mode used for the vr4102/vr4111 is: generic #2 (external chip select, shared read/write enable for high byte, individual read/write enable for low byte). host bus pin connection the following table shows the functions of each host bus interface signal. for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. generic #2 interface mode generic #2 interface mode is a general and non-processor-speci? interface mode on the s1d13705. the generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the vr4102/vr4111 control signals. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we1# is the high byte enable for both read and write cycles. we0# is the write enable for the s1d13705, to be driven low when the host cpu is writing data to the s1d13705. rd# is the read enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. table 7-1 host bus interface pin mapping s1d13705 pin names generic #2 ab[15:1] a[15:1] ab0 a0 db[15:0] d[15:0] we1# bhe# cs# external decode bclk bclk bs# connect to io v dd rd/wr# connect to io v dd rd# rd# we0# we# wait# wait# reset# reset# 7: interfacing to the nec vr4102/vr4111 microprocessor s1d13705f00a application notes epson 5-47 (x27a-g-008-01) wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers and/or refresh memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) and read/write (rd/wr#) signals are not used in the bus interface for generic #2 mode. however, bs# is used to con?ure the s1d13705 for generic #2 mode and should be tied high (connected to io v dd ). rd/wr# should also be tied high. 7.4 vr4102/vr4111 to s1d13705 interface hardware description the nec vr4102/vr4111 microprocessor is speci?ally designed to support an external lcd controller by providing the internal address decoding and control signals necessary. by using the generic # 2 interface, no glue logic is required to interface the s1d13705 and the nec vr4102/ vr4111. a pull-up resistor is attached to wait# to speed up its rise time when terminating a cycle. the following diagram shows a typical implementation of the vr4102/vr4111 to s1d13705 interface. figure 7-2 typical implementation of vr4102/vr4111 to s1d13705 interface we1# we0# db[15:0] wait# rd# busclk s1d13705 cs# reset# ab[16:0] shb# wr# data[15:0] lcdcs# rd# busclk lcdrdy add[16:0] nec vr4102/vr4111 pull-up bs# rd/wr# vcc vcc system reset note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 7: interfacing to the nec vr4102/vr4111 microprocessor 5-48 epson s1d13705f00a application notes (x27a-g-008-01) s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02 for details. the tables below show those con?uration settings important to the generic #2 host bus interface. nec vr4102/vr4111 con?uration the nec vr4102/vr4111 provides the internal address decoding necessary to map to an external lcd controller. physical address 0a000000h to 0affffffh (16m bytes) is reserved for an external lcd controller. the s1d13705 supports up to 80k bytes of display buffer memory and 32 bytes for internal registers. therefore, the s1d13705 will be shadowed over the entire 16m byte memory range at 128k byte segments. the starting address of the display buffer is 0a000000h and register 0 of the s1d13705 (reg[00h]) resides at 0a01ffe0h. the nec vr4102/vr4111 has a 16-bit internal register named bcucntreg2 located at address 0b000002h. it must be set to the value of 0001h to indicate that lcd controller accesses use a non- inverting data bus. the 16-bit internal register named bcucntreg1, located at address 0b000000h, must have bit d[13] (isa/lcd bit) set to 0 to reserve the 16m bytes space, 0a000000h to 0affffffh, for lcd use and not as isa bus memory space. 7.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. table 7-2 summary of power-on/reset options signal value on this pin at the rising edge of reset# is used to con?ure: (0/1) 01 cnf0 see ?ost bus interface selection?table7-3 below. see ?ost bus interface selection?table7-3 below. cnf1 cnf2 cnf3 little endian big endian = con?uration for nec vr4102/vr4111 support table 7-3 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 1 1 1 1 generic #2, 16-bit = con?uration for nec vr4102/vr4111 support 8: interfacing to the nec vr4181a tm microprocessor s1d13705f00a application notes epson 5-49 (x27a-g-013-01) 8i nterfacing to the nec vr4181a tm m icroprocessor 8.1 introduction this application note describes the hardware required to interface the s1d13705 embedded memory lcd controller and the nec vr4181a microprocessor. the nec vr4181a microprocessor is speci?ally designed to support an external lcd controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. 8.2 interfacing to the nec vr4181a the nec vr4181a system bus the vr-series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. designed with external lcd controller support and windows ce based embedded consumer applications in mind, the vr4181a offers a highly integrated solution for portable systems. this section is an overview of the operation of the cpu bus to establish interface requirements. overview the nec vr4181a is designed around the risc architecture developed by mips. this microprocessor is designed around the 100mhz vr4110 cpu core which supports the mips iii and mips16 instruction sets. the cpu communicates with external devices via an isa interface. the nec vr4181a has direct support for an external lcd controller. a 64 to 512-kilobyte block of memory is assigned to the lcd controller with a dedicated chip select signal. word or byte accesses are controlled by the system high byte signal, #ube. lcd memory access signals the s1d13705 requires an addressing range of 128kbytes. when the vr4181a s external lcd controller chip select signal is programmed to a window of that size, the s1d13705 must reside in the vr4181a physical address range of 133e 0000h to 133f ffffh which is part of the external isa memory space. the signals required for external lcd controller access are listed below and obey isa signalling rules. a[16:0]address bus #ubehigh byte enable (active low) #lcdcslcd controller (s1d13705) chip select (active low) d[15:0]data bus #memrdread command (active low) #memwrwrite command (active low) #memcs16sixteen-bit peripheral capability acknowledge (active low) iordyready signal from s1d13705 sysclkoptional, prescalable bus clock x27a-g-013-01 8: interfacing to the nec vr4181a tm microprocessor 5-50 epson s1d13705f00a application notes (x27a-g-013-01) once an address in the lcd block of memory is accessed, the lcd chip select #lcdcs is driven low. the read or write enable signals, #memrd or #memwr, are driven low for the appropriate cycle and iordy is driven low by the s1d13705 to insert wait states into the cycle. the high byte enable is driven low for 16-bit transfers and high for 8-bit transfers. 8.3 s1d13705 host bus interface this section is a summary of the host bus interface modes available on the s1d13705 that would be used to interface to the vr4181a. the s1d13705 implements a 16-bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families. the interface mode used for the vr4181a is: generic #2 (external chip select, shared read/write enable for high byte, individual read/write enable for low byte). host bus pin connection for details on con?uration, refer to the ?1d13705 hardware functional speci?ation , document number x27a-a-001-02. generic #2 interface mode generic #2 interface mode is a general and non-processor-speci? interface mode on the s1d13705. the generic # 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the vr4181a control signals. the interface requires the following signals: busclk is a clock input which synchronizes transfers between the host cpu and the s1d13705. it is separate from the input clock (clki) and is typically driven by the host cpu system clock. the address inputs ab0 through ab16, and the data bus db0 through db15, connect directly to the cpu address and data bus, respectively. on 32-bit big endian architectures such as the power pc, the data bus would connect to the high-order data lines; on little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data lines. the hardware engineer must ensure that cnf3 selects the proper endian mode upon reset. chip select (cs#) is driven by decoding the high-order address lines to select the proper register and memory address space. we1# is the high byte enable for both read and write cycles. table 8-1 host bus interface pin mapping s1d13705 pin names generic #2 ab[16:1] a[16:1] ab0 a0 db[15:0] d[15:0] we1# bhe# cs# external decode bclk bclk bs# connect to io v dd rd/wr# connect to io v dd rd# rd# we0# we# wait# wait# reset# reset# 8: interfacing to the nec vr4181a tm microprocessor s1d13705f00a application notes epson 5-51 (x27a-g-013-01) we0# is the write enable signal for the s1d13705, to be driven low when the host cpu is writing data from the s1d13705. rd# is the read enable for the s1d13705, to be driven low when the host cpu is reading data from the s1d13705. wait# is a signal which is output from the s1d13705 to the host cpu that indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. since host cpu accesses to the s1d13705 may occur asynchronously to the display update, it is possible that contention may occur in accessing the s1d13705 internal registers or memory. the wait# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. this signal is active low and may need to be inverted if the host cpu wait state signal is active high. the bus status (bs#) and read/write (rd/wr#) signals are not used in the bus interface for generic #2 mode. however, bs# is used to con?ure the s1d13705 for generic #2 mode and should be tied high (connected to iov dd ). rd/wr# should also be tied high. 8.4 vr4181a to s1d13705 interface hardware description the nec vr4181a microprocessor is speci?ally designed to support an external lcd controller by providing the internal address decoding and control signals necessary. by using the generic # 2 interface, a glueless interface is achieved. the diagram below shows a typical implementation of the vr4181a to s1d13705 interface. figure 8-1 typical implementation of vr4181a to s1d13705 interface we1# we0# db[15:0] wait# rd# bclk s1d13705 cs# reset# ab[15:0] #ube #memwr d[15:0] #lcdcs #memrd iordy a[16:0] nec vr4181a pull-up bs# rd/wr# vcc vcc system reset oscillator #memcs16 note: when connecting the s1d13705 reset# pin, the system designer should be aware of all conditions that may reset the s1d13705 (e.g. cpu reset can be asserted during wake-up from power-down modes, or during debug states). 8: interfacing to the nec vr4181a tm microprocessor 5-52 epson s1d13705f00a application notes (x27a-g-013-01) the host interface control signals of the s1d13705 are asynchronous with respect to the s1d13705 bus clock. this gives the system designer full ?xibility to choose the appropriate source (or sources) for clki and bclk. the choice of whether both clocks should be the same, and whether an external or internal clock divider is needed, should be based on the desired: pixel and frame rates. power budget. part count. maximum s1d13705 clock frequencies. the s1d13705 also has internal clock dividers providing additional ?xibility. s1d13705 hardware con?uration the s1d13705 uses cnf3 through cnf0 and bs# to allow selection of the bus mode and other con?uration data on the rising edge of reset#. refer to the ?1d13705 hardware functional speci?ation ? document number x27a-a-001-02 for details. the tables below show those con?uration settings important to the generic #2 host bus interface. nec vr4181a con?uration the nec vr4181a must be con?ured through its internal registers in order to map the s1d13705 to the external lcd controller space. the following register values must be set. register lcdgpmd at address 0b00 032eh must be set as follows. bit 7 must be set to 1 to disable the internal lcd controller and enable the external lcd controller interface. this also maps pin shclk to #lcdcs and pin loclk to #memcs16. bits [1:0] must be set to 01b to reserve 128kbytes of memory address range 133e 0000h to 133f ffffh for the external lcd controller. register gpmd2reg at address 0b00 0304h must be set as follows. bits [9:8] (gp20md[1:0]) must be set to 11b to map pin gpio20 to #ube. bits [5:4] (gp18md[1:0]) must be set to 01b to map pin gpio18 to iordy. table 8-2 summary of power-on/reset options signal value on this pin at the rising edge of reset# is used to con?ure: (0/1) 01 cnf0 see ?ost bus interface selection?table8-3 below. see ?ost bus interface selection?table8-3 below. cnf1 cnf2 cnf3 little endian big endian = con?uration for nec vr4181a support table 8-3 host bus interface selection cnf2 cnf1 cnf0 bs# host bus interface 1 1 1 1 generic #2, 16-bit = con?uration for nec vr4181a support 8: interfacing to the nec vr4181a tm microprocessor s1d13705f00a application notes epson 5-53 (x27a-g-013-01) 8.5 software test utilities and windows ce v2.0 display drivers are available for the s1d13705. full source code is available for both the test utilities and the drivers. the test utilities are con?urable for different panel types using a program called 1375cfg, or by directly modifying the source. the windows ce v2.0 display drivers can be customized by the oem for different panel types, resolutions and color depths only by modifying the source. 9: s1d13705 power consumption 5-54 epson s1d13705f00a application notes (x27a-g-006-01) 9 s1d13705 p ower c onsumption 9.1 s1d13705 power consumption s1d13705 power consumption is affected by many system design variables. input clock frequency (clki): the clki frequency and the internal clock divide register deter- mine the operating clock (clk) frequency of the s1d13705. the higher clk is, the higher the frame fate, performance, and power consumption. cpu interface: the s1d13705 current consumption depends on the busclk frequency, data width, number of toggling pins, and other factors ?the higher the busclk, the higher the cpu performance and power consumption. ? dd voltage levels (core and io): the voltage level of the core and io sections in the s1d13705 affects power consumption ?the higher the voltage, the higher the consumption. display mode: the resolution, panel type, and color depth affect power consumption. the higher the resolution/color depth and number of lcd panel signals, the higher the power consumption. note: if the high performance option is turned on, the power consumption increases to that of 8 bit- per-pixel mode for all color depths. there are two power save modes in the s1d13705: software and hardware power save. the power consumption of these modes is affected by various system design variables. cpu bus state during power save: the state of the cpu bus signals during power save has a sub- stantial effect on power consumption. an inactive bus (e.g. busclk = low, addr = low etc.) reduces overall system power consumption. clki state during power save: disabling the clki during power save has substantial power sav- ings. x27a-g-006-01 9: s1d13705 power consumption s1d13705f00a application notes epson 5-55 (x27a-g-006-01) conditions table 9-1 below gives an example of a speci? environment and its effects on power consumption. note: 1. conditions for software power save: ?cpu interface active (signals toggling) ?clki active 2. conditions for hardware power save: ?cpu interface inactive (high impedance) ?clki active 9.2 summary the system design variables in section 9.1, ?1d13705 power consumption?and in table 9-1 show that s1d13705 power consumption depends on the speci? implementation. active mode power consumption depends on the desired cpu performance and lcd frame-rate, whereas power save mode consumption depends on the cpu interface and input clock state. in a typical design environment, the s1d13705 can be con?ured to be an extremely power-ef?ient lcd controller with high performance and ?xibility. table 9-1 s1d13705 total power consumption test condition core v dd = 3.3v, io v dd = 3.3v busclk = 8.33mhz gray shades / colors power consumption active power save mode core io total software hardware 1 input clock = 6mhz lcd panel = 320x240 4-bit single mono- chrome black-and-white 4 gray shades 16 gray shades 4.29mw 4.99mw 6.13mw 0.52mw 0.76mw 0.75mw 4.81mw 5.75mw 6.88mw 1.44mw 1 1.21mw 2 2 input clock = 6mhz lcd panel = 320x240 4-bit single color 2 colors 4 colors 16 colors 256 colors 4.64mw 5.30mw 6.58mw 8.65mw 0.73mw 1.51mw 1.57mw 1.52mw 5.37mw 6.81mw 8.15mw 10.16mw 1.44mw 1 1.22mw 2 3 input clock = 25mhz lcd panel = 640x480 8-bit single mono- chrome black-and-white 4 gray shades 13.97mw 16.75mw 1.10mw 2.08mw 15.07mw 18.83mw 2.53mw 1 2.32mw 2 4 input clock = 25mhz lcd panel = 640x480 8-bit single color 2 colors 4 colors 15.53mw 18.30mw 2.64mw 7.16mw 18.17mw 25.47mw 2.53mw 1 2.32mw 2 5 input clock = 25mhz lcd panel = 640x480 8-bit dual mono- chrome black-and-white 4 grey shades 13.84mw 20.38mw 1.08mw 2.07mw 14.93mw 22.45mw 2.53mw 1 2.32mw 2 6 input clock = 25mhz lcd panel = 640x480 8-bit dual color 2 colors 4 colors 15.82mw 23.31mw 2.62mw 7.01mw 18.44mw 30.32mw 2.53mw 1 2.32mw 2 7 input clock = 25mhz lcd panel = 640x480 9-bit tft 2 colors 4 colors 11.42mw 19.74mw 7.40mw 20.96mw 18.82mw 40.70mw 2.53mw 1 2.32mw 2 9: s1d13705 power consumption 5-56 epson s1d13705f00a application notes (x27a-g-006-01) this page is blank. s1d13705f00a embedded memory lcd controller windows ce display drivers contents s1d13705f00a windows ce display epson 6-i drivers contents 1 w indows ce d isplay d rivers ...............................................................................................6-1 1.1 program requirements ...................................................................................................... ............. 6-1 1.2 example driver builds ..................................................................................................... ................ 6-1 build for cepc (x86) for windows ce versions 2.0 thru 2.1 .................................................. 6-1 build for cepc (x86) for windows ce version 2.11 (platform builder) .................................. 6-2 1.3 example installation ...................................................................................................... .................. 6-4 installation for cepc environment ............................................................................................. 6 -4 1.4 comments .................................................................................................................. ..................... 6-4 1: windows ce display drivers s1d13705f00a windows ce display epson 6-1 drivers (x27a-e-001-01) 1 windows ce d isplay d rivers the windows ce display drivers are designed to support the s1d13705 embedded memory lcd controller running under the microsoft windows ce operating system. available drivers include: 4 and 8 bit-per-pixel landscape modes, and 4 and 8 bit-per-pixel portrait modes. 1.1 program requirements 1.2 example driver builds build for cepc (x86) for windows ce versions 2.0 thru 2.1 to build a windows ce v2.0 or v2.1 display driver for the cepc (x86) platform using an s5u13705b00c evaluation board, follow the instructions below: 1. install microsoft windows nt v4.0. 2. install microsoft visual c/c++ v5.0. 3. install the microsoft windows ce embedded toolkit (etk) by running setup.exe from the etk compact disc #1. 4. create a new project by following the procedure documented in ?reating a new project directory?from the windows ce etk v 2.0. alternately, use the current ?emo7?project included with the etk v2.0. follow the steps below to create a ?86 demo7?shortcut on the windows nt v4.0 desktop which uses the current ?emo7?project: a. right click on the ?tart?menu on the taskbar. b. click on the item ?pen all users?and the ?tart menu?window will come up. c. click on the icon ?rograms? d. click on the icon ?indows ce embedded development kit? e. drag the icon ?86 demo1?onto the desktop using the right mouse button. f. click on ?opy here? g. rename the icon ?86 demo1?on the desktop to ?86 demo7?by right clicking on the icon and choosing ?ename? h. right click on the icon ?86 demo7?and click on ?roperties?to bring up the ?86 demo7 properties?window. i. replace the string ?emo1?under the entry ?arget?with ?emo7? j. click on ?k?to ?ish. 5. create a sub-directory named 8bpp1375 under \wince\platform\cepc\drivers\display. 6. copy the source code to the 8bpp1375 subdirectory. 7. add an entry for the 8bpp1375 in the ?e \wince\platform\cepc\drivers\display\dirs. 8. since the s5u13705b00c maps memory to 0xf00000, the cepc machine should use the cmos setup to create a 1m byte hole from address 0xf00000 to 0xffffff. video controller : s1d13705 display type : lcd or crt windows version : ce versions 2.0 thru 2.11 1: windows ce display drivers 6-2 epson s1d13705f00a windows ce display drivers (x27a-e-001-01) 9. edit the ?e platform.bib (located in x:\wince\platform\cepc\?es) to set add the display driver 8bpp1375.dll. 8bpp1375.dll will be created during the build in step 11. add the following lines in platform.bib: if cepc_ddi_8bpp1375 ddi.dll $(_flatreleasedir)\8bpp13705.dllnk sh endif before these lines: if cepc_ddi_vga2bpp ddi.dll $(_flatreleasedir)\ddi_vga2.dllnk sh endif if cepc_ddi_vga8bpp ddi.dll $(_flatreleasedir)\ddi_vga8.dllnk sh endif and this line: if cepc_ddi_8bpp1375 ! before these lines that test before dropping into the default display driver: if cepc_ddi_vga2bpp ! if cepc_ddi_vga8bpp ! ddi.dll $(_flatreleasedir)\ddi_s364.dllnk sh endif endif and ?ally to match the added if: endif 10. generate the proper building environment by double-clicking on the sample project icon (i.e. x86 demo7). 11. type blddemo 1: windows ce display drivers s1d13705f00a windows ce display epson 6-3 drivers (x27a-e-001-01) set cepc_ddi_8bpp1375=1 @echo off. 5. install 1375 cepc driver a. copy 1375 driver into \wince211\platform\cepc\drivers\display\8bpp1375 a. add 8bpp1375 into the directory list in ?e \wince211\platform\cepc\drivers\display\dirs 6. edit the ?e platform.bib (located in x:\wince211\platform\cepc\?es) to add a display driver for 8bpp1375.dll. 8bpp1375.dll will be created during the build in step 9. add the following lines in platform.bib: if cepc_ddi_8bpp1375 ddi.dll $(_flatreleasedir)\8bpp1375.dllnk sh endif before these lines: if cepc_ddi_vga8bpp ddi.dll $(_flatreleasedir)\ddi_vga8.dllnk sh endif and this line: if cepc_ddi_8bpp1375 ! before these lines that test before dropping into the default display driver: if cepc_ddi_vga8bpp ! ddi.dll $(_flatreleasedir)\ddi_s364.dllnk sh endif and ?ally add an endif after the ?st endif to match the added if: endif 7. cleanup platform builder as normal (remove the \wince211\release directory and delete \wince211\platform\cepc\*.bif). 8. generate the proper building environment by selecting ?uild maxall for x86?from the start menu. you should see an echo of the lines added earlier to maxall.bat: set wincerel=1 set cepc_ddi_8bpp1375=1 9. type blddemo 1: windows ce display drivers 6-4 epson s1d13705f00a windows ce display drivers (x27a-e-001-01) 1.3 example installation installation for cepc environment windows ce v2.0 can be loaded on a pc using a ?ppy drive or a hard drive. the two methods are described below: 1. to load cepc from a ?ppy drive: a. create a dos bootable ?ppy disk. b. edit config.sys on the ?ppy disk to contain the following line only. device=a:\himem.sys c. edit autoexec.bat on the ?ppy disk to contain the following lines. mode com1:9600,n,8,1 loadcepc /b:9600 /c:1 /d:2 c:\wince\release\nk.bin d. copy loadcepc.exe from c:\wince\public\common\oak\bin to the bootable ?ppy disk. e. con?m that nk.bin is located in c:\wince\release. f. reboot the system from the bootable ?ppy disk. 2. to load cepc from a hard drive: a. copy loadcepc.exe to the root directory of the hard drive. b. edit config.sys on the hard drive to contain the following line only. device=c:\himem.sys c. edit autoexec.bat on the hard drive to contain the following lines. mode com1:9600,n,8,1 loadcepc /b:9600 /c:1 /d:2 c:\wince\release\nk.bin d. con?m that nk.bin is located in c:\wince\release. e. reboot the system from the hard drive. 1.4 comments alternatively, in the examples above, you could substitute 4bpp instead of 8bpp. on some cepc systems creating the 1m byte address hole will cause loadcepc.exe to fail. in this case contact your sales representative for a newer version of loadcepc.exe called load211x.exe. america epson electronics america, inc. - headquarters - 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-408-922-0200 fax: +1-408-922-0238 - sales offices - west 1960 e. grand avenue ei segundo, ca 90245, u.s.a. phone: +1-310-955-5300 fax: +1-310-955-5400 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone: +1-815-455-7630 fax: +1-815-455-7633 northeast 301 edgewater place, suite 120 wakefield, ma 01880, u.s.a. phone: +1-781-246-3600 fax: +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone: +1-877-eea-0020 fax: +1-770-777-2637 europe epson europe electronics gmbh - headquarters - riesstrasse 15 80992 munich, germany phone: +49-(0)89-14005-0 fax: +49-(0)89-14005-110 sales office altstadtstrasse 176 51379 leverkusen, germany phone: +49-(0)2171-5045-0 fax: +49-(0)2171-5045-10 uk branch office unit 2.4, doncastle house, doncastle road bracknell, berkshire rg12 8pe, england phone: +44-(0)1344-381700 fax: +44-(0)1344-381701 french branch office 1 avenue de l' atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone: +33-(0)1-64862350 fax: +33-(0)1-64862355 barcelona branch office barcelona design center edificio testa avda. alcalde barrils num. 64-68 e-08190 sant cugat del vall s, spain phone:+34-93-544-2490 fax:+34-93-544-2491 international sales operations asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: 64106655 fax: 64107319 shanghai branch 4f, bldg., 27, no. 69, gui jing road caohejing, shanghai, china phone: 21-6485-5552 fax: 21-6485-0775 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 10f, no. 287, nanking east road, sec. 3 taipei phone: 02-2717-7360 fax: 02-2712-9164 telex: 24444 epsontb hsinchu office 13f-3, no. 295, kuang-fu road, sec. 2 hsinchu 300 phone: 03-573-9900 fax: 03-573-9169 epson singapore pte., ltd. no. 1 temasek avenue, #36-00 millenia tower, singapore 039192 phone: +65-337-7911 fax: +65-334-2716 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: 02-784-6027 fax: 02-767-3677 seiko epson corporation electronic devices marketing division electronic device marketing department ic marketing & engineering group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5816 fax: +81-(0)42-587-5624 ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5812 fax: +81-(0)42-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5814 fax: +81-(0)42-587-5110 in pursuit of ?aving technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings . mf1213-02 s1d13705f00a technical manual technical manual s1d13705f00a technical manual embedded memory lcd controller s1d13705f00a epson electronic devices website electronic devices marketing division http://www.epson.co.jp/device/ first issue august, 1999 d printed july, 2001 in japan c b this manual was made with recycle papaer, and printed using soy-based inks. |
Price & Availability of S1D13305F00A100
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |